Abstract: A method performed by a tablet device having a touch screen display and at least one sensor coupled to a processor includes using the at least one sensor to determine that a cover attached to the tablet device is in a partially open configuration, receiving a touch input gesture from an uncovered portion of the touch screen display when the cover is in the partially open configuration, identifying, based upon a type of the input gesture, an operating parameter of the device, determining, based upon the input gesture, a setting value for the operating parameter, and altering the operating parameter of the device based upon the setting value. For example, the gesture can be a swipe, the operating parameter can be a brightness of the display, and altering the operating parameter can include adjusting the brightness of the display based upon the value.

Abstract: A mechanism for protecting integrated circuits (IC) from security attacks includes an IC having components that may store one or more data items and may perform a number of functions and which produce resulting events. The IC may also include a security module that may modify signals and events provided to the components such that the resulting events are modified in a non-effectual way but that causes the events to be non-deterministic relative to an event that is external to the integrated circuit when the resulting events are viewed externally to the IC. This may result in obscuring the data, and the functions from being observed from external to the IC, particularly when using an IR laser probe.

Abstract: A mechanism for protecting integrated circuits (IC) from security attacks includes an IC having components that may store one or more data items and may perform a number of functions and which produce resulting events. The IC may also include a security module that may modify signals and events provided to the components such that the resulting events are modified in a non-effectual way but that causes the events to be non-deterministic relative to an event that is external to the integrated circuit when the resulting events are viewed externally to the IC. This may result in obscuring the data, and the functions from being observed from external to the IC, particularly when using an IR laser probe.

Abstract: A method performed by a tablet device having a touch screen display and at least one sensor coupled to a processor includes using the at least one sensor to determine that a cover attached to the tablet device is in a partially open configuration, receiving a touch input gesture from an uncovered portion of the touch screen display when the cover is in the partially open configuration, identifying, based upon a type of the input gesture, an operating parameter of the device, determining, based upon the input gesture, a setting value for the operating parameter, and altering the operating parameter of the device based upon the setting value. For example, the gesture can be a swipe, the operating parameter can be a brightness of the display, and altering the operating parameter can include adjusting the brightness of the display based upon the value.

Abstract: A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.

Abstract: A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.

Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Abstract: The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.

Abstract: A method and apparatus for random-access scan of a network 990 of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates (900) driven by multiple overlapping clock signals generated from a clock generation circuit (904) coupled to a clock spine (902). Each clocked precharge logic gate and each scan gate include a logic tree (502) with one or more evaluate nodes, a precharge circuit (32), an evaluate circuit (36), and one or more output buffers (34). Each scan gate further includes a scan circuit (806) that accepts scan control signals (406, 408, 410, 824, and 826) and couples to one or more scan registers (416) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

Abstract: This invention discloses a software tool 20 that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool 20 includes a routing rule generation tool 22 that creates a route rule database 30 for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool 32 that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool 22. The routing rule generation tool 22 further includes a noise sensitivity/gate characterization tool 24 and a rule generator tool 28. The block build tool 32 further includes a gate sizing tool 34, a gate analysis tool 36, a route rule selecting tool 38, a route assigning tool 42.

Abstract: A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.

Abstract: This invention discloses a software tool 20 that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool 20 includes a routing rule generation tool 22 that creates a route rule database 30 for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool 32 that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool 22. The routing rule generation tool 22 further includes a noise sensitivity/gate characterization tool 24 and a rule generator tool 28. The block build tool 32 further includes a gate sizing tool 34, a gate analysis tool 36, a route rule selecting tool 38, a route assigning tool 42.

Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Abstract: A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers.

Abstract: The present invention is a method and apparatus that initializes N-NARY logic and dynamic logic to a special stress mode. The present invention has a logic circuit that includes a shared logic tree with one or more evaluate nodes, one or more precharge devices, and an evaluate device. Coupled to the evaluate nodes is a state generation control circuit that generates a state signal. A state generation circuit receives the state signal from the state generation control circuit and initializes the evaluate nodes to a functionally illegal state that initializes the logic circuit to the special stress mode. One embodiment of the present invention initializes the evaluate nodes to a low state. When the first logic circuit in a series of logic circuits is initialized to the functionally illegal state, the present invention will initialize the succeeding logic circuits in the series as each phase in the different clock domains evaluate, which initializes the succeeding logic circuits to the special stress mode.

Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.

Abstract: A method and apparatus for random-access scan of a network 990 of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates (900) driven by multiple overlapping clock signals generated from a clock generation circuit (904) coupled to a clock spine (902). Each clocked precharge logic gate and each scan gate include a logic tree (502) with one or more evaluate nodes, a precharge circuit (32), an evaluate circuit (36), and one or more output buffers (34). Each scan gate further includes a scan circuit (806) that accepts scan control signals (406, 408, 410, 824, and 826) and couples to one or more scan registers (416) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Abstract: The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.

Abstract: A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers.