Abstract: A gated clock driver is configured to provide an enable signal and a gated clock signal at each of a plurality flip-flops. One of the p-channel transistors of the gated clock driver's NOR gate is distributed to each of the flip-flops or latches in the system. Additionally, an extra n-channel transistor is provided in the gated clock circuit to form an inverter with the nondistributed p-channel transistor. More particularly, the p-channel transistor that is driven by the system clock input is distributed to each of the flip-flops. Similarly, the enable input (at the output of the new inverter) is distributed to each of the flip-flops. Since the gated clock signal cannot be generated without the enable signal being high and the system clock being low, distributing enable and the p-channel transistor which receives the system clock as an input minimizes clock skew as compared to flip-flops with a completely shared clock gating clock.

Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.

Abstract: A digital clock waveform generator and method for generating a clock signal are provided for a microprocessor or other digital circuit to provide on chip generation of internal clock signals having the same frequency as or a higher or lower frequency than an externally applied clock signal. In one embodiment, the waveform generator includes a delay chain and a control unit that matches the propagation delay of the delay chain to the period of an input timing signal. The waveform generator provides precise control of the duty cycles of the internally generated clock signals, and allows for rapid starting and stopping of the internal clock signals for power reduction functions. The waveform generator may further provide a system clock, and may include circuitry to precisely control the phase relationships between the various clock signals.

Abstract: A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.

Abstract: A variable strength clock signal driver circuit and method of manufacturing the same are provided that accommodate either full or reduced drive strength of a generated clock signal. The clock driver circuit includes a package bonding option to select the desired strength of drive. Thus, the clock driver circuit may be operated at either fast or slow clock frequencies as determined by the system requirements. As a result, both high performance, high drive versions and low cost, low drive versions of a digital circuit such as a microprocessor may be provided that differ only in package bonding. The same set of masks may be used to produce either version of the circuit, thus permitting greater manufacturing flexibility and reducing cost. Furthermore, electromagnetic interference may be reduced by selecting the low drive strength option for cost sensitive applications.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain to be compared with respect to one another. The delay chain is employed within a clock generator circuit that generates internal clock signals of a microprocessor. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. During a test operation when it is desired to test the variable delay units for possible defects, the four delay units are electrically separated from one another by setting the multiplexers in a test mode. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: A distributed clock generation scheme is provided for a microprocessor that reduces electromagnetic interference and power consumption. Rather than using a single, large internal clock generator circuit that meets the drive requirements of the remaining circuitry upon the microprocessor die, a plurality of smaller clock generator circuits are distributed across the die, each generating clock signals to drive a separate portion of the microprocessor circuitry. Each of the distributed clock generator circuits may be load matched with respect to the others to minimize the skew between clock signals, and each receives a synchronized timing signal provided from a master timing distribution circuit. As a result of the distributed clock generation scheme, the amount of current and the rate at which current is sourced or sunk at a given location on the semiconductor die is reduced, thereby reducing electromagnetic interference and increasing the signal to noise ratio.

Abstract: A variable strength clock signal driver circuit and method of manufacturing the same are provided that accommodate either full or reduced drive strength of a generated clock signal. The clock driver circuit includes a package bonding option to select the desired strength of drive. Thus, the clock driver circuit may be operated at either fast or slow clock frequencies as determined by the system requirements. As a result, both high performance, high drive versions and low cost, low drive versions of a digital circuit such as a microprocessor may be provided that differ only in package bonding. The same set of masks may be used to produce either version of the circuit, thus permitting greater manufacturing flexibility and reducing cost. Furthermore, electromagnetic interference may be reduced by selecting the low drive strength option for cost sensitive applications.

Abstract: A variable drive strength buffer circuit is provided that automatically adjusts its associated drive strength to compensate for variations in manufacturing parameters, environmental conditions and operating conditions. As a result, electromagnetic interference, power supply noise, edge rates and ringing may be reduced. The self-adjusting variable drive buffer circuit may be fabricated on an integrated circuit and includes a speed detector unit that measures the relative speed of the integrated circuit. In one embodiment, a self-adjusting variable drive strength buffer circuit includes a circuit speed detector unit having a delay chain consisting of a plurality of variable delay elements. When the delay chain length is matched to the period of an input clock, the length of the chain is an accurate measure of the relative "speed" of the transistors making up the delay chain and therefore of the other transistors on the integrated circuit chip.

Abstract: A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time.

Abstract: Apparatus and method of a data cache which provides for the handling of errors during data copy-back from a data cache write buffer to external memory in a processing system including a processor. When data requested by the processor at an addressed storage location of the data cache is data which is valid, modified, and other than the data requested by the processor, the data is first transferred to the data cache write buffer and then written back to external memory after the requested data is fetched from a memory bus. If an error occurs during the write back of the data from the write buffer to external memory, the data is transferred from the write buffer to the storage location of the data cache originally addressed by the processor before the memory bus is released.

Abstract: There is disclosed an interlock variable acquisition system and method for use in a processing system of the type including a plurality of processors coupled by a common bus which permits exclusive execution of critical sections by each of the processors while limiting traffic on the common bus. A cache associated with each of the processors stores the value of the interlock variable and locally tests the interlock variable state responsive to an instruction from its processor. If the cache determines that the interlock variable is in the available state, it conveys the available value of the interlock variable to its associated processor and writes, over the common bus, the busy state to each cache associated with the other processors. When its processor completes its critical section, the cache writes, over the common bus, the available state of the interlock variable to each cache associated with the other processors.