Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

Abstract: Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

Abstract: Integrated circuitry comprising transistor structures having a channel portion over a base portion of fin. The base portion of the fin is an insulative amorphous oxide, or a counter-doped crystalline material. Transistor structures, such as channel portions of a fin and source and drain materials may be first formed with epitaxial processes seeded by a front side of a crystalline substrate. Following front side processing, a backside of the transistor structures may be exposed and the base portion of the fin modified from the crystalline substrate composition into the amorphous oxide or counter-doped crystalline material using backside processes and low temperatures that avoid degradation to the channel material while reducing transistor off-state leakage.

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Abstract: Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.

Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.