Patents by Inventor Stephen Cea
Stephen Cea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11495683Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.Type: GrantFiled: February 19, 2020Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Patrick Keys, Sayed Hasan, Stephen Cea, Anupama Bowonder
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Patent number: 11367722Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.Type: GrantFiled: September 21, 2018Date of Patent: June 21, 2022Assignee: Intel CorporationInventors: Aaron Lilak, Stephen Cea, Gilbert Dewey, Willy Rachmady, Roza Kotlyar, Rishabh Mehandru, Sean Ma, Ehren Mannebach, Anh Phan, Cheng-Ying Huang
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Publication number: 20220157984Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA
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Patent number: 11276780Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.Type: GrantFiled: June 29, 2018Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Rishabh Mehandru, Tahir Ghani, Stephen Cea
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Publication number: 20210257492Abstract: Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.Type: ApplicationFiled: February 19, 2020Publication date: August 19, 2021Applicant: Intel CorporationInventors: Aaron Lilak, Patrick Keys, Sayed Hasan, Stephen Cea, Anupama Bowonder
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Publication number: 20210202534Abstract: Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Inventors: Chung-Hsun LIN, Biswajeet GUHA, William HSU, Stephen CEA, Tahir GHANI
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Publication number: 20210159312Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.Type: ApplicationFiled: January 8, 2021Publication date: May 27, 2021Applicant: Intel CorporationInventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
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Patent number: 10892326Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.Type: GrantFiled: March 30, 2017Date of Patent: January 12, 2021Assignee: Intel CorporationInventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
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Publication number: 20200411640Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Rishabh MEHANDRU, Stephen CEA, Anupama BOWONDER, Juhyung NAM, Willy RACHMADY
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Publication number: 20200303509Abstract: Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.Type: ApplicationFiled: March 22, 2019Publication date: September 24, 2020Applicant: Intel CorporationInventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA
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Publication number: 20200219997Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.Type: ApplicationFiled: January 3, 2019Publication date: July 9, 2020Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA, Biswajeet GUHA
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Publication number: 20200105871Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Glenn GLASS, Anand MURTHY, Biswajeet GUHA, Dax M. CRUM, Sean MA, Tahir GHANI, Susmita GHOSE, Stephen CEA, Rishabh MEHANDRU
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Publication number: 20200105753Abstract: Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.Type: ApplicationFiled: September 27, 2018Publication date: April 2, 2020Inventors: Roza KOTLYAR, Rishabh MEHANDRU, Stephen CEA, Biswajeet GUHA, Dax CRUM, Tahir GHANI
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Publication number: 20200098756Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.Type: ApplicationFiled: September 21, 2018Publication date: March 26, 2020Applicant: INTEL CORPORATIONInventors: Aaron Lilak, Stephen Cea, Gilbert Dewey, Willy Rachmady, Roza Kotlyar, Rishabh Mehandru, Sean Ma, Ehren Mannebach, Anh Phan, Cheng-Ying Huang
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Publication number: 20200006332Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Cory BOMBERGER, Anand MURTHY, Stephen CEA, Biswajeet GUHA, Anupama BOWONDER, Tahir GHANI
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Publication number: 20200006546Abstract: A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Rishabh MEHANDRU, Tahir GHANI, Stephen CEA
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Publication number: 20190333990Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.Type: ApplicationFiled: March 30, 2017Publication date: October 31, 2019Applicant: Intel CorporationInventors: Aaron Lilak, Patrick Keys, Sean Ma, Stephen Cea, Rishabh Mehandru
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Publication number: 20170263853Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices and spin logic devices, wherein a strain engineered interface is formed within at least one magnet within these devices. In one embodiment, the spin transfer torque memory devices may include a free magnetic layer stack comprising a crystalline magnetic layer abutting a crystalline stressor layer. In another embodiment, the spin logic devices may include an input magnet, an output magnet; wherein at least one of the input magnet and the output magnet comprises a crystalline magnetic layer abutting crystalline stressor layer and/or the crystalline magnetic layer abutting a crystalline spin-coherent channel extending between the input magnet and the output magnet.Type: ApplicationFiled: September 3, 2014Publication date: September 14, 2017Applicant: INTEL CORPORATIONInventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri Nikonov, David Michalak, Stephen Cea, Ian Young
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Publication number: 20070034945Abstract: Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.Type: ApplicationFiled: October 24, 2006Publication date: February 15, 2007Inventors: Mark Bohr, Tahir Ghani, Stephen Cea, Kaizad Mistry, Christopher Auth, Mark Armstrong, Keith Zawadzki
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Patent number: 7045408Abstract: An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.Type: GrantFiled: May 21, 2003Date of Patent: May 16, 2006Assignee: Intel CorporationInventors: Thomas Hoffmann, Chris Auth, Mark Armstrong, Stephen Cea