Patents by Inventor Stephen E. Greco
Stephen E. Greco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7301236Abstract: An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.Type: GrantFiled: October 18, 2005Date of Patent: November 27, 2007Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Chao-Kun Hu, Paul S. McLaughlin
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Patent number: 7135398Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.Type: GrantFiled: July 29, 2004Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: John A. Fitzsimmons, Stephen E. Greco, Jia Lee, Stephen M. Gates, Terry Spooner, Matthew S. Angyal, Habib Hichri, Theordorus E. Standaert, Glenn A. Biery
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Patent number: 7101784Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.Type: GrantFiled: May 10, 2005Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
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Patent number: 7071099Abstract: Methods of forming different back-end-of-line (BEOL) wiring for different circuits on the same semiconductor product, i.e., wafer or chip, are disclosed. In one embodiment, the method includes simultaneously generating BEOL wiring over a first circuit using a dual damascene structure in a first dielectric layer, and BEOL wiring over a second circuit using a single damascene via structure in the first dielectric layer. Then, simultaneously generating BEOL wiring over the first circuit using a dual damascene structure in a second dielectric layer, and BEOL wiring over the second circuit using a single damascene line wire structure in the second dielectric layer. The single damascene via structure has a width approximately twice that of a via portion of the dual damascene structures and the single damascene line wire structure has a width approximately twice that of a line wire portion of the dual damascene structures.Type: GrantFiled: May 19, 2005Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Theodorus E. Standaert
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Patent number: 6921978Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.Type: GrantFiled: May 8, 2003Date of Patent: July 26, 2005Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
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Patent number: 6917108Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.Type: GrantFiled: November 14, 2002Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: John A. Fitzsimmons, Stephen E. Greco, Jia Lee, Stephen M. Gates, Terry Spooner, Matthew S. Angyal, Habib Hichri, Theordorus E. Standaert, Glenn A. Biery
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Publication number: 20040259035Abstract: An integrated circuit, a fuse therefor and fuse opening method are disclosed. The method implements fuse opening using a wet etchant. As a result, there is no explosion that causes damage to surrounding material. In addition, use of the wet etchant allows positioning of a fuse in any metal layer including any non-last metal layer, thus increasing design possibilities.Type: ApplicationFiled: June 20, 2003Publication date: December 23, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Stephen E. Greco
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Publication number: 20040224494Abstract: The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features.Type: ApplicationFiled: May 8, 2003Publication date: November 11, 2004Applicant: International Business Machines CorporationInventors: Lawrence A. Clevenger, Stephen E. Greco, Keith T. Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang, Kwong H. Wong
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Publication number: 20040094511Abstract: A method for controlling the shape of copper features, having the following steps:Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Applicant: International Business Machines CorporationInventors: Soon-Cheon Seo, Wei-Tsu Tseng, Darryl D. Restaino, James E. Fluegel, Richard O. Henry, John M. Cotte, Mahadevaiyer Krishnan, Hariklia Deligianni, Philippe Mark Vereecken, Stephen E. Greco
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Publication number: 20040094839Abstract: An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.Type: ApplicationFiled: November 14, 2002Publication date: May 20, 2004Applicant: International Business Machines CorporationInventors: John A. Fitzsimmons, Stephen E. Greco, Jia Lee, Stephen M. Gates, Terry Spooner, Matthew S. Angyal, Habib Hichri, Theordorus E. Standaert, Glenn A. Biery
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Patent number: 6734096Abstract: A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 Å, preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.Type: GrantFiled: January 17, 2002Date of Patent: May 11, 2004Assignee: International Business Machines CorporationInventors: Timothy J. Dalton, Minakshisundaran B. Anand, Michael D. Armacost, Shyng-Tsong Chen, Stephen M. Gates, Stephen E. Greco, Simon M. Karecki, Satyanarayana V. Nitta
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Patent number: 6727589Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: November 30, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20030134505Abstract: A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 Å, preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.Type: ApplicationFiled: January 17, 2002Publication date: July 17, 2003Applicant: International Business Machines CorporationInventors: Timothy J. Dalton, Minakshisundaran B. Anand, Michael D. Armacost, Shyng-Tsong Chen, Stephen M. Gates, Stephen E. Greco, Simon M. Karecki, Satyanarayana V. Nitta, Anna Karecki
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Patent number: 6479884Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: June 29, 2001Date of Patent: November 12, 2002Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6348736Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes.Type: GrantFiled: October 29, 1999Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Vincent J. McGahay, John P. Hummel, Joyce Liu, Rebecca Mih, Kamalesh Srivastava, Robert Cook, Stephen E. Greco
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Patent number: 6339022Abstract: A method for increasing the production yield of semiconductor devices having copper metallurgy planarized by a chemical-mechanical planarization process which includes a slurry that contains a conductor passivating agent, like benzotriazole, wherein a non-oxidizing anneal is used to remove any residue which might interfere with mechanical probing of conductive lands on the substrate prior to further metallization steps. The anneal may be performed by any of several techniques including a vacuum chamber, a standard furnace or by rapid thermal annealing.Type: GrantFiled: December 30, 1999Date of Patent: January 15, 2002Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Edward C. Cooney, III, George A. Dunbar, III, Cheryl G. Faltermeier, Jeffrey D. Gilbert, Ronald D. Goldblatt, Nancy A. Greco, Stephen E. Greco, Frank V. Liucci, Glenn Robert Miller, Bruce A. Root, Andrew H. Simon, Anthony K. Stamper, Ronald A. Warren, David H. Yao
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Patent number: 6329280Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: May 13, 1999Date of Patent: December 11, 2001Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010036739Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: ApplicationFiled: June 29, 2001Publication date: November 1, 2001Inventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6221780Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: September 29, 1999Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010000115Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer nay be either a single damascene or a dual damascene layer.Type: ApplicationFiled: November 30, 2000Publication date: April 5, 2001Inventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava