Patents by Inventor Stephen E. Greco
Stephen E. Greco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10169525Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.Type: GrantFiled: June 9, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Vincent J. McGahay, Rasit O. Topaloglu
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Patent number: 10152567Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.Type: GrantFiled: January 5, 2018Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Rasit O. Topaloglu
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Publication number: 20180129774Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.Type: ApplicationFiled: January 5, 2018Publication date: May 10, 2018Inventors: Stephen E. Greco, Rasit O. Topaloglu
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Patent number: 9940429Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.Type: GrantFiled: June 29, 2015Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Rasit O. Topaloglu
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Publication number: 20170277823Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.Type: ApplicationFiled: June 9, 2017Publication date: September 28, 2017Inventors: Stephen E. Greco, Vincent J. McGahay, Rasit O. Topaloglu
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Patent number: 9710592Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.Type: GrantFiled: October 14, 2015Date of Patent: July 18, 2017Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Vincent J. McGahay, Rasit O. Topaloglu
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Patent number: 9601367Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.Type: GrantFiled: March 25, 2013Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen E. Greco, Rasit O. Topaloglu
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Patent number: 9589912Abstract: A first aspect of the disclosure provides for an integrated circuit structure. The integrated circuit structure may comprise a first metal structure in a first dielectric layer on a substrate in a crack stop area; and a first crack stop structure in a second dielectric layer, the first crack stop structure being over the first metal structure and including: a first metal fill contacting the first metal structure; and an air seam substantially separating the first metal fill and the second dielectric layer.Type: GrantFiled: August 27, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jim S. Liang, Atsushi Ogino, Stephen E. Greco, Roger A. Quon
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Patent number: 9589911Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.Type: GrantFiled: August 27, 2015Date of Patent: March 7, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jim S. Liang, Atsushi Ogino, Roger A. Quon, Stephen E. Greco
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Publication number: 20170062355Abstract: A first aspect of the disclosure provides for an integrated circuit structure. The integrated circuit structure may comprise a first metal structure in a first dielectric layer on a substrate in a crack stop area; and a first crack stop structure in a second dielectric layer, the first crack stop structure being over the first metal structure and including: a first metal fill contacting the first metal structure; and an air seam substantially separating the first metal fill and the second dielectric layer.Type: ApplicationFiled: August 27, 2015Publication date: March 2, 2017Inventors: Jim S. Liang, Atsushi Ogino, Stephen E. Greco, Roger A. Quon
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Publication number: 20170062354Abstract: Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.Type: ApplicationFiled: August 27, 2015Publication date: March 2, 2017Inventors: Jim S. Liang, Atsushi Ogino, Roger A. Quon, Stephen E. Greco
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Publication number: 20160378904Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: Stephen E. Greco, Rasit O. Topaloglu
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Patent number: 9454631Abstract: Via-level design shapes are mapped into stitch regions of line-level design shapes design in an overlying conductive line level. A via-catching design shape is provided in an underlying conductive line level for each stitch region that does not correspond to a via-level design shape. The shapes of the stitch regions and the via-catch design shapes can be adjusted to comply with design rule constraints. Further, stitches can be optionally moved into a neighboring line-level design shape to resolve design rule conflicts. The modified design layout can eliminate via-level design shapes once all via-level design shapes are replaced with a corresponding stitch region, thereby eliminating the need to provide a via level lithographic mask. A metal interconnect structure embodying the modified design layout can be formed by employing a set of hard mask layers and without employing a lithographic mask for a via level.Type: GrantFiled: May 23, 2014Date of Patent: September 27, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen E. Greco, Vincent J. McGahay, Rasit O. Topaloglu
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Patent number: 9455186Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.Type: GrantFiled: May 26, 2015Date of Patent: September 27, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
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Patent number: 9424388Abstract: In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, a computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines the one or more exposure areas in the reticle field, and at least one lithography process parameter for each exposure area of the one or more exposure areas in the reticle field based, at least in part, on the data received from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.Type: GrantFiled: December 17, 2014Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Stephen E. Greco, Rasit O. Topaloglu
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Patent number: 9406560Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.Type: GrantFiled: May 26, 2015Date of Patent: August 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
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Patent number: 9385038Abstract: A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.Type: GrantFiled: May 26, 2015Date of Patent: July 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp, Thomas W. Dyer, Ronald G. Filippi, Stephen E. Greco, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20160180003Abstract: In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, the computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines one or more exposure areas in the reticle field, and at least one lithography process parameter for each of the one or more exposure areas in the reticle field based, at least in part, on the data from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.Type: ApplicationFiled: December 17, 2014Publication date: June 23, 2016Inventors: Stephen E. Greco, Rasit O. Topaloglu
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Patent number: 9373538Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.Type: GrantFiled: October 2, 2015Date of Patent: June 21, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen E. Greco, Rasit O. Topaloglu
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Publication number: 20160042114Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.Type: ApplicationFiled: October 14, 2015Publication date: February 11, 2016Inventors: Stephen E. Greco, Vincent J. McGahay, Rasit O. Topaloglu