Abstract: A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Abstract: A system and method of recovering from errors in a data processing system. The data processing system includes one or more processor cores coupled to one or more memory controllers. The one or more memory controllers include at least a first memory interface coupled to a first memory and at least a second memory interface coupled to a second memory. In response to determining an error has been detected in the first memory, access to the first memory via the first memory interface is inhibited. Also, the first memory interface is locally restarted without restarting the second memory interface.

Abstract: In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Setting of busy latches at the outset virtually eliminates the chance of collisions, and status bits are set to inform the requesting core processor that a command is done and free of error, if that is the case.

Abstract: Vibratory welded connections are formed between first and second members of thermoplastic material by interposing a junction piece of similar material and vibrating the junction piece at high speed while pressing the first and second members in a controlled manner against opposite sides of the junction piece. Friction created by the vibration generates heat which melts a small amount of material at the engaging surfaces which upon cooling provides a strong welded joint having minimal flash. Entire frame systems such as window frames can be fabricated by an apparatus system which forms a friction welded joint between adjacent ends of the frame members. Furthermore the frame can be fabricated around a panel such as a glazing panel. The welded connections formed by the system do not mar the finish of the frame members and produce no unsightly flash bead requiring subsequent machining steps for its removal.

Abstract: A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes and a given cache way shared between the two cache slices, and if one a cache way is defective that is part of a first cache line in the first cache slice and part of a second cache line in the second cache slice, it is disabled while continuing to use at least one other cache way which is also part of the first cache line and part of the second cache line. In the illustrative embodiment the cache array is set associative and at least two different cache ways for a given cache line contain different congruence classes for that cache line. The defective cache way can be disabled by preventing an eviction mechanism from allocating any congruence class in the defective way. For example, half of the cache line can be disabled (i.e., half of the congruence classes).

Abstract: Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering is enabled for the device memory address ranges. Transfer operations are processed to transfer data to contiguous device memory addresses in the device. A determination is made as to whether the indicator bits for the contiguous device memory addresses indicate that gathering is enabled. A single bus I/O transaction is generated to transfer data for the contiguous device memory addresses over the I/O bus in response to determining that the indicator bits for the contiguous device memory addresses indicate that gathering is enabled.

Abstract: A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

Abstract: A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

Abstract: A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

Abstract: A method, apparatus and computer instructions are provided to autonomically monitor and adjust system characteristics based on a customer optimization goal specified in a policy or profile. An autonomic management component is implemented in firmware comprising a set of control algorithms. Response to reading system characteristics from a plurality of sensors, the autononmic management component selects at least one control algorithm from the set and the control algorithm adjusts the parameters of the system characteristic to optimize performance according to the optimization goal specified by the customer.

Abstract: A framed panel and related method of manufacture are disclosed. A framed panel unit includes a panel along the edge of which thermoplastic frame members are disposed. The frame members have first and second opposed side walls which define a channel for receiving the edge of the panel. The channel of each frame member has spacers between the panel and each side wall for spacing the panel from the side walls. Prior to welding together the ends of the frame members, the spacers retain the frame members on the panel. The panel may include multiple opposed sheet members with a spacer between the sheet members spacing them apart, and a reactive thermoplastic sealant material bonding the sheets to the frame members. An associated method of forming a named panel, frame members for a panel, and a spacer component for use in mounting a panel within a channel of a frame member are also disclosed.

Abstract: A vibration welding element for thermoplastic members, and related joint structures, assemblies, and methods, are disclosed. A vibration welding element that is composed at least in part of a thermoplastic material includes at least one welding surface for forming a vibratory welded bond with at least one thermoplastic member. The element also includes a component holder that is physically coupled to the welding surface for enabling the element to hold a further component. The component holder may also be held in a fixture of a vibratory head during a vibratory welding process by which a vibratory welded bond is formed.

Abstract: Vibratory welded connections are formed between first and second members of thermoplastic material by interposing a junction piece of similar material and vibrating the junction piece at high speed while pressing the first and second members in a controlled manner against opposite sides of the junction piece. Friction created by the vibration generates heat which melts a small amount of material at the engaging surfaces which upon cooling provides a strong welded joint having minimal flash. Entire frame systems such as window frames can be fabricated by an apparatus system which forms a friction welded joint between adjacent ends of the frame members. Furthermore the frame can be fabricated around a panel such as a glazing panel. The welded connections formed by the system do not mar the finish of the frame members and produce no unsightly flash bead requiring subsequent machining steps for its removal.

Abstract: The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

Abstract: Methods, data processing systems, and program products are disclosed that support the definition and accessing of links indicating a relationship between configuration construct instances, such as Dial and Dial group instances, within a digital design. According to one method, first and second latches within the digital design are specified in at least one HDL statement within one or more HDL files representing the digital design. In the one or more HDL files, a first configuration construct instance referencing the first latch and a second configuration construct instance referencing the second latch are also defined. The first and second configuration construct instances provide interfaces through which values of the first and second latches can be accessed. In addition, a link indicating a relationship between the first and second configuration construct instances is also defined within the one or more HDL files.

Abstract: Vibratory welded connections are formed between first and second members of thermoplastic material by interposing a junction piece of similar material and vibrating the junction piece at high speed while pressing the first and second members in a controlled manner against opposite sides of the junction piece. Friction created by the vibration generates heat which melts a small amount of material at the engaging surfaces which upon cooling provides a strong welded joint having minimal flash. Entire frame systems such as window frames can be fabricated by an apparatus system which forms a friction welded joint between adjacent ends of the frame members. Furthermore the frame can be fabricated around a panel such as a glazing panel. The welded connections formed by the system do not mar the finish of the frame members and produce no unsightly flash bead requiring subsequent machining steps for its removal.

Abstract: Vibratory welded connections are formed between first and second members (32, 33) of thermoplastic material by interposing a junction piece (47) of similar material and vibrating the junction piece (47) at high speed while pressing the first second members (32,33) in a controlled manner against opposite sides of the junction piece (47). Friction created by the vibration generates heat which melts a small amount of material at the engaging surfaces which upon cooling provides a strong welded joint having minimal flash. Entire frame systems such as window-frames can be fabricated by an apparatus system (120) which forms a friction welded joint between adjacent ends of the frame members (134, 135, 136, 137). Furthermore the frame can be fabricated around a panel such as a glazing panel. The welded connections formed by the system do not mar the finish of the frame members and produce no unsightly flash bead requiring subsequent machining steps for its removal.

Abstract: An apparatus and method for accurately tuning the speed of an integrated circuit, i.e. a computer chip, using a built-in sense circuit and controller are provided. The sense circuit is provided in association with a monitored path. The sense circuit includes a variable delay element coupled to a controller. A data signal from the monitored path is provided to the sense circuit which adds an amount of delay as determined by the controller to the data signal. The delayed data signal and the original data signal are compared to determine if their values match. If they match, then the amount of delay added by the variable delay element is increased. If they do not match, then a previous amount of delay, prior to the mismatch, is output as the slack of the monitored path. The slack may then be used to tune the speed of the integrated circuit.

Abstract: A method and system for speculatively pre-fetching data from a memory. A memory controller on a data bus “snoops” data requests put on the data bus by a bus control logic. Based on information in the header of the data request, such as transaction type, tag, transaction size, etc., a speculative pre-fetch is made to read data from the memory associated with the memory controller. If the speculative fetch turns out to be correct, then the memory controller makes an assumption that the pre-fetch was too conservative (non-speculative), and a pre-fetch for a next data request is performed at an earlier more speculative time. If the speculative fetch turns out to be incorrect, then the memory controller makes an assumption that the pre-fetch was too speculative (made early), and a pre-fetch for a next data request is performed at a later less speculative time.

Abstract: A support structure (10) for supporting a plurality of antennas (11) has a plurality of antenna supports (13) each for supporting at least one antenna (11). Each antenna support (13) is supported for rotation about an axis of rotation. At least one antenna support (13) is selectively rotatable with respect to the or each other antenna support (13) such that an antenna (11) supported by said at least one antenna support (13) rotates therewith.