Patents by Inventor Stephen Hanna
Stephen Hanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940926Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.Type: GrantFiled: May 13, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventor: Stephen Hanna
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Patent number: 11941300Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.Type: GrantFiled: October 21, 2022Date of Patent: March 26, 2024Inventors: Giuseppe D'Eliseo, Luca Porzio, Stephen Hanna
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Publication number: 20240053905Abstract: Methods, systems, and devices for compression and decompression of trim data are described. A memory system may store one or more trim settings to a volatile memory in a compressed manner, and may expand (e.g., decompress) the data as part of a write operation to a non-volatile memory (e.g., during a start-up procedure). For example, compressed (e.g., non-expanded) data including trim settings may be stored to a volatile memory, and a portion of the array of volatile memory cells may be temporarily allocated to expand the data (e.g., copy the data, invert the data, copy the inverted data). Once the data is expanded, it may be stored in the non-volatile memory, and the temporarily allocated portion of the array of volatile memory cells may be reallocated (e.g., allocated for another purpose). The expanded data may include multiple copies and inverted copies of the trim settings.Type: ApplicationFiled: August 15, 2022Publication date: February 15, 2024Inventors: Reshmi Basu, Jonathan S. Parry, Giuseppe Cariello, Stephen Hanna
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Publication number: 20240045617Abstract: Methods, systems, and devices for address verification at a memory system are described. A memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. For example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. The memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. The address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.Type: ApplicationFiled: August 8, 2022Publication date: February 8, 2024Inventor: Stephen Hanna
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Publication number: 20240045812Abstract: A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.Type: ApplicationFiled: October 18, 2023Publication date: February 8, 2024Inventor: Stephen Hanna
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Publication number: 20240045596Abstract: Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.Type: ApplicationFiled: August 4, 2022Publication date: February 8, 2024Inventors: Reshmi Basu, Jonathan S. Parry, David Aaron Palmer, Luca Porzio, Giuseppe Cariello, Stephen Hanna
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Publication number: 20240020033Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.Type: ApplicationFiled: September 11, 2023Publication date: January 18, 2024Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
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Publication number: 20230367718Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.Type: ApplicationFiled: May 13, 2022Publication date: November 16, 2023Inventor: Stephen Hanna
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Patent number: 11815939Abstract: A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.Type: GrantFiled: May 19, 2022Date of Patent: November 14, 2023Inventor: Stephen Hanna
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Patent number: 11809311Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.Type: GrantFiled: August 9, 2021Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: David Aaron Palmer, Christian M. Gyllenskog, Jonathan Scott Parry, Stephen Hanna
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Patent number: 11775207Abstract: Methods, systems, and devices for techniques to perform a write operation are described. In response to receiving a sequential write command from a host system, the memory system may determine non-linear offsets for a set of requests for portions of the data. The memory system may determine a first subset of the data that includes data segments having logical addresses with gaps corresponding to the offset between the data segments to store in a first memory device. The memory system may store the first subset in a buffer and program the first subset to the first memory device. Additionally, the memory system may determine a second subset of data that using the offset and may transmit a second set of requests for the second subset of data, which may be stored in the buffer and programmed to a second memory device.Type: GrantFiled: February 15, 2022Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventor: Stephen Hanna
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Publication number: 20230305617Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.Type: ApplicationFiled: January 12, 2023Publication date: September 28, 2023Inventors: Luca Porzio, Christian M. Gyllenskog, Giuseppe Cariello, Marco Onorato, Roberto IZZI, Stephen Hanna, Jonathan S. Parry, Reshmi Basu, Nadav Grosz, David Aaron Palmer
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Patent number: 11755214Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.Type: GrantFiled: March 23, 2022Date of Patent: September 12, 2023Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Scott Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
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Publication number: 20230267047Abstract: Methods, systems, and devices for device reset alert mechanism are described. The memory system may identify a fault condition associated with resetting the memory system and set, in a register associated with event alerts of the memory system, a first indication for a reset of the memory system. In some cases, the memory system may transmit a message that includes a second indication that the register associated with event alerts of the memory system has been changed based on setting the register.Type: ApplicationFiled: May 6, 2022Publication date: August 24, 2023Inventor: Stephen Hanna
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Publication number: 20230259304Abstract: Methods, systems, and devices for techniques to perform a write operation are described. In response to receiving a sequential write command from a host system, the memory system may determine non-linear offsets for a set of requests for portions of the data. The memory system may determine a first subset of the data that includes data segments having logical addresses with gaps corresponding to the offset between the data segments to store in a first memory device. The memory system may store the first subset in a buffer and program the first subset to the first memory device. Additionally, the memory system may determine a second subset of data that using the offset and may transmit a second set of requests for the second subset of data, which may be stored in the buffer and programmed to a second memory device.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventor: Stephen Hanna
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Patent number: 11704256Abstract: An example memory subsystem includes a memory component and a processing device, operatively coupled to the memory component. The processing device is configured to receive a plurality of logical-to-physical (L2P) records, wherein an L2P record of the plurality of L2P records maps a logical block address to a physical address of a memory block on the memory component; determine a sequential assist value specifying a number of logical block addresses that are mapped to consecutive physical addresses sequentially following the physical address specified by the L2P record; generate a security token encoding the sequential assist value; and associate the security token with the L2P record.Type: GrantFiled: November 8, 2021Date of Patent: July 18, 2023Assignee: Micron Technology, Inc.Inventors: Stephen Hanna, Nadav Grosz
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Patent number: 11656673Abstract: A memory device includes a hardware suspend mechanism configured to place a component of a memory controller into a lower power mode while a memory operation is being completed. A timer is provided to wakeup the CPU out of the lower power mode; and hardware interrupts can be used in determining to either enter or wake from the lower power mode. Memory monitoring circuitry is provided to estimate the duration of memory operations; and timers are provided to wake the component in the absence of hardware interrupts or additional commands.Type: GrantFiled: December 29, 2020Date of Patent: May 23, 2023Assignee: Micron Technology, Inc.Inventors: Qing Liang, Jonathan Scott Parry, David Aaron Palmer, Stephen Hanna
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Publication number: 20230111015Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.Type: ApplicationFiled: October 21, 2022Publication date: April 13, 2023Inventors: Giuseppe D'Eliseo, Luca Porzio, Stephen Hanna
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Patent number: 11568953Abstract: An example system comprises: a master bus electrically coupled to a master multiplexer controlled by a test mode signal selecting between a master physical interface (PHY) and a slave bus of a plurality of slave buses, wherein each slave bus is electrically coupled to a respective slave multiplexer selecting between a respective slave PHY and the master bus; a plurality of electrical circuits, wherein each electrical circuit of the plurality of electrical circuits is electrically coupled to one of: the master bus or a slave bus of the plurality of slave buses; and a memory test interface electrically coupled to the master bus.Type: GrantFiled: January 19, 2021Date of Patent: January 31, 2023Assignee: Micron Technology, Inc.Inventor: Stephen Hanna
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Publication number: 20230027877Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.Type: ApplicationFiled: October 4, 2022Publication date: January 26, 2023Inventors: Qing Liang, Jonathan S. Parry, Kulachet Tanpairoj, Stephen Hanna