Patents by Inventor Stephen Hanna
Stephen Hanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10871907Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.Type: GrantFiled: December 31, 2018Date of Patent: December 22, 2020Assignee: Micron Technology, Inc.Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
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Publication number: 20200210080Abstract: Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.Type: ApplicationFiled: December 31, 2018Publication date: July 2, 2020Inventors: David Aaron Palmer, Sean L. Manion, Jonathan Parry, Stephen Hanna, Qing Liang, Nadav Grosz, Christian M. Gyllenskog, Kulachet Tanpairoj
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Publication number: 20200201785Abstract: A memory device comprises a memory array including memory cells, a communication interface to a host device, and a memory control unit operatively coupled to the memory array and the communication interface. The memory control unit is configured to generate a scrambler seed and a logical block address (LBA) for a block of write data received via the communication interface, scramble the block of data using the scrambler seed, encrypt the scrambler seed and the LBA using an encryption key, initiate writing a scrambled block of data and encrypted LBA and scrambler seed to the memory array, and change the encryption key in response to an erase command received via the communication interface.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventor: Stephen Hanna
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Publication number: 20200192814Abstract: Apparatus and methods are disclosed, including using a memory controller to generate an encoded physical address using a run length encoding (RLE) algorithm on a physical address to reduce a length of the encoded physical address, and storing the encoded physical address as a map entry of a logical-to-physical (L2P)) table in a cache random access memory of the memory controller.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Inventors: Stephen Hanna, Nadav Grosz
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Patent number: 10664168Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.Type: GrantFiled: November 27, 2018Date of Patent: May 26, 2020Assignee: Seagate Technology LLCInventors: Timothy Canepa, Stephen Hanna
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Patent number: 10353622Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.Type: GrantFiled: March 2, 2017Date of Patent: July 16, 2019Assignee: SEAGATE TECHNOLOGY LLCInventors: Erich F. Haratsch, Zhengang Chen, Stephen Hanna, Abdelhakim Alhussien
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Patent number: 10248330Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.Type: GrantFiled: May 30, 2017Date of Patent: April 2, 2019Assignee: Seagate Technology LLCInventors: Jackson Ellis, Jeffrey Munsil, Timothy Canepa, Stephen Hanna
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Publication number: 20190095099Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Timothy Canepa, Stephen Hanna
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Patent number: 10229052Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.Type: GrantFiled: May 31, 2017Date of Patent: March 12, 2019Assignee: Seagate Technology LLCInventors: Timothy Canepa, Ryan J. Goss, Stephen Hanna
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Patent number: 10229000Abstract: Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.Type: GrantFiled: August 9, 2016Date of Patent: March 12, 2019Assignee: Seagate LLCInventors: Timothy Canepa, Stephen Hanna
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Publication number: 20180349266Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Timothy Canepa, Ryan J. Goss, Stephen Hanna
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Publication number: 20180349035Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.Type: ApplicationFiled: May 30, 2017Publication date: December 6, 2018Inventors: Jackson Ellis, Jeffrey Munsil, Timothy Canepa, Stephen Hanna
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Publication number: 20180341403Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Inventors: Timothy Canepa, Stephen Hanna
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Patent number: 10140027Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.Type: GrantFiled: May 26, 2017Date of Patent: November 27, 2018Assignee: Seagate Technology LLCInventors: Timothy Canepa, Stephen Hanna
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Publication number: 20180306336Abstract: A check valve comprising a valve body having a central bore a hinge pin a blocking means pivotably attached to the hinge pin and moveable between a first position in which the blocking means blocks the central bore and a second position in which the blocking means does not block the central bore, and a biasing means arranged to bias the blocking means into the first position, wherein the valve body comprises at least one boss projecting from an inner wall of the valve body into the central bore, and wherein said boss provides an anchoring point at which the hinge pin is secured to the valve body.Type: ApplicationFiled: April 20, 2018Publication date: October 25, 2018Inventors: Simon LUSTY, Stephen HANNA, Ranjit BHALKAR
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Patent number: 9905294Abstract: Method and apparatus for managing data in a data storage device. In some embodiments, a non-volatile cache memory stores a sequence of pages from a host device. A non-volatile main memory has a plurality of n-level cells arranged on m separate integrated circuit dies each simultaneously accessible during programming and read operations using an associated transfer circuit, where m and n are plural numbers. A control circuit writes first and second pages from the sequence of pages to a selected set of the n-level cells coupled to a common word line on a selected integrated circuit die. The second page is separated from the first page in the sequence of pages by a logical offset comprising a plurality of intervening pages in the sequence of pages. The logical offset is selected responsive to the m number of integrated circuit dies and a delay time associated with the transfer circuits.Type: GrantFiled: May 3, 2017Date of Patent: February 27, 2018Assignee: Seagate Technology LLCInventors: Timothy L. Canepa, Alex Tang, Stephen Hanna
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Publication number: 20180046543Abstract: Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.Type: ApplicationFiled: August 9, 2016Publication date: February 15, 2018Inventors: Timothy Canepa, Stephen Hanna
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Publication number: 20170177236Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: ERICH F. HARATSCH, ZHENGANG CHEN, STEPHEN HANNA, ABDELHAKIM ALHUSSIEN
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Publication number: 20170102991Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.Type: ApplicationFiled: October 8, 2015Publication date: April 13, 2017Applicant: SEAGATE TECHNOLOGY LLCInventors: ERICH F. HARATSCH, ZHENGANG CHEN, STEPHEN HANNA, ABDELHAKIM ALHUSSIEN
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Patent number: 9619321Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.Type: GrantFiled: October 8, 2015Date of Patent: April 11, 2017Assignee: SEAGATE TECHNOLOGY LLCInventors: Erich F. Haratsch, Zhengang Chen, Stephen Hanna, Abdelhakim Alhussien