Abstract: A method and apparatus is provided for locating with improved vertical positioning accuracy a discrete element on a semiconductor optoelectronic integrated circuit. The method employs an etch stop layer located beneath a series of semiconductor layers. The semiconductor layers may include waveguides to couple light between integrated or discrete elements. Pits with accurate depth are etched in the semiconductor layers down to the etch stop layer. Accurate alignment between a discrete element and another element is made possible by controlling their respective distances from the etch stop layer.

Abstract: A gate controlled lateral bipolar junction transistor (GCLBJT) device for an integrated circuit and a method of fabrication thereof are provided. The GCLBJT resembles a merged field effect transistor and lateral bipolar transistor, i.e. a lateral bipolar transistor having base, emitter and collector terminals and a fourth terminal for controlling a gate electrode overlying an active base region. The device is operable as an electronically configurable lateral transistor. Advantageously a heavily doped buried layer provides a base electrode having a base contact which surrounds and encloses the collector. The surface region between emitter and collector is characterized by lightly doped regions adjacent and contiguous with the heavily doped emitter and collector, which effectively reduce the base width of the bipolar transistor and improve operation for analog applications.

Abstract: A method and apparatus are provided for coupling light from a fiber to a waveguide on an OEIC (optoelectronic integrated circuit). The region of the fiber to be connected is made into a D-fiber by removing a portion of its cladding. The flat surface is fused to a silicon dioxide coated portion of the waveguide. The light in the fiber is evanescently coupled into the waveguide on the OEIC which is typically a planar or channel waveguide.

Abstract: A channel waveguide structure which can be incorporated into VLSI (very large scale integration) integrated circuits uses a SiGe (silicon germanium) alloy core and Si (silicon) top and bottom cladding layers. The core may consist of only a SiGe alloy layer or it may be formed as a superlattice containing Si layers alternating with SiGe alloy layers. LOCOS (locally oxidized silicon) regions are formed on the top cladding layer at spaced locations thereby defining lateral boundaries of channels in the core.

Abstract: A lateral bipolar transistor is provided in which the active base region comprises a layer of a material providing a predetermined valence band offset relative to the emitter and collector regions, to enhance transport of carriers from the emitter to the collector in a lateral manner. In particular, a silicon hetero-junction lateral bipolar transistor (HLBT) is provided. The lateral bipolar transistor structure and method of fabrication of the transistor is compatible with a bipolar-CMOS integrated circuit. Preferably the base region comprises a silicon-germanium alloy or a silicon-germanium superlattice structure comprising a series of alternating layers of silicon and silicon-germanium alloy.