Patents by Inventor Stephen J. Robinson

Stephen J. Robinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210117372
    Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 22, 2021
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
  • Patent number: 10901940
    Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: January 26, 2021
    Assignee: INTEL CORPORATION
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
  • Publication number: 20200319886
    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.
    Type: Application
    Filed: February 24, 2020
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Christopher J. Hughes, Joseph Nuzman, Jonas Svennebring, Doddaballapur N. Jayasimha, Samantika S. Sury, David A. Koufaty, Niall D. McDonnell, Yen-Cheng Liu, Stephen R. Van Doren, Stephen J. Robinson
  • Patent number: 10572260
    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Joseph Nuzman, Jonas Svennebring, Doddaballapur N. Jayasimha, Samantika S. Sury, David A. Koufaty, Niall D. McDonnell, Yen-Cheng Liu, Stephen R. Van Doren, Stephen J. Robinson
  • Publication number: 20190205139
    Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Christopher J. Hughes, Joseph Nuzman, Jonas Svennebring, Doddaballapur N. Jayasimha, Samantika S. Sury, David A. Koufaty, Niall D. McDonnell, Yen-Cheng Liu, Stephen R. Van Doren, Stephen J. Robinson
  • Patent number: 10067762
    Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Vikash Agarwal, Christopher D. Bryant, Jonathan D. Combs, Stephen J. Robinson
  • Patent number: 9996487
    Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jose S. Niell, Daniel F. Cutter, Stephen J. Robinson, Mukesh K. Patel
  • Patent number: 9875187
    Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 23, 2018
    Assignee: Intel Corporation
    Inventors: Christopher D. Bryant, Stephen J. Robinson
  • Publication number: 20180004522
    Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: VIKASH AGARWAL, CHRISTOPHER D. BRYANT, JONATHAN D. COMBS, STEPHEN J. ROBINSON
  • Patent number: 9785576
    Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Thiam Wah Loh, Per Hammarlund, Andreas Wasserbauer, Swee Chong Peter Kuan, Eckhard Delfs, Deepak A. Mathaikutty, Stephen J. Robinson, Gautham N. Chinya, Perry H. Wang, Chee Weng Tan, Hong Wang, Reza Fortas
  • Publication number: 20170286113
    Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.
    Type: Application
    Filed: April 2, 2016
    Publication date: October 5, 2017
    Applicant: INTEL CORPORATION
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson, Christopher D. Bryant, Jason W. Brandt
  • Patent number: 9632907
    Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Beeman C. Strong, Stephen J. Robinson, Jason W. Brandt, Peter Lachner
  • Patent number: 9619412
    Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson
  • Publication number: 20160378701
    Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.
    Type: Application
    Filed: June 26, 2015
    Publication date: December 29, 2016
    Inventors: Jose S. Niell, Daniel F. Cutter, Stephen J. Robinson, Mukesh K. Patel
  • Patent number: 9454371
    Abstract: A computer system and processor for elimination of move operations include circuits that obtain a computer instruction and bypass execution units in response to determining that the instruction includes a move operation that involves a transfer of data from a logical source register to a logical destination register. Instead of executing the move operation, the transfer of the data is performed by tracking changes in data dependencies of the source and the destination registers, and assigning a physical register associated with the source register to the destination register based on the dependencies.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Venkateswara Madduri, Jonathan Combs, James E. Phillips, Stephen J. Robinson, James D. Allen, Jonathan J. Tyler
  • Publication number: 20160170888
    Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: CHRISTOPHER D. BRYANT, STEPHEN J. ROBINSON
  • Publication number: 20160170820
    Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Inventors: BEEMAN C. STRONG, STEPHEN J. ROBINSON, JASON W. BRANDT, PETER LACHNER
  • Publication number: 20150347168
    Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 3, 2015
    Inventors: Vedvyas Shanbhogue, Stephen J. Robinson
  • Patent number: 9189360
    Abstract: A method is described that involves referring to first information from a directory table in system memory. The first information includes location information and size information of a first slice of system memory where first tracing data is to be stored. The method also includes tracking the amount of tracing data stored in the first slice of system memory and comparing the amount against the size information. The method also includes, before the first slice of system memory is filled, referring to second information from the directory table in system memory, where, the second information includes location information and size information of a second slice of system memory where second tracing data is to be stored. The first slice is not contiguous with the second slice of system memory.
    Type: Grant
    Filed: June 15, 2013
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Beeman C. Strong, Jason W. Brandt, Tsvika Kurts, Peter Lachner, Itamar Kazachinsky, Stephen J. Robinson, Peggy J. Irelan
  • Publication number: 20150277949
    Abstract: A processing system includes an interconnect and a processing core, coupled to the interconnect, to execute a plurality of virtual machines each being identified by a respective identifier, and tag, by an identifier of the first virtual machine, a first transaction initiated by a first virtual machine to access the interconnect.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: THIAM WAH LOH, GAUTHAM N. CHINYA, STEPHEN J. ROBINSON, REZA FORTAS, HONG WANG, HELMUT REINIG, PER HAMMARLUND, DEEPAK A. MATHAIKUTTY, CHRISTIAN ERBEN