Abstract: Support systems and stands for electronic devices include tilt hinges, lift arms, and their component parts. Some tilt hinges include assemblies for guiding and retaining bars or protrusions into preferred positioning within receiver openings to unify the parts, particularly as they move, and to reduce wobble or slop in the joints. Lift arms provide simplified and low-cost guidance and counterbalance mechanisms for controlling movement of the electronic device relative to the base of a stand. In some cases, the lift arms have sheaths to help protect or cover mechanisms while allowing additional space for the mechanisms within the lift arm. Other interconnection systems hide and protect a connector interface between the stand and the electronic device within a housing until unlocked and the connector is moved into an exposed position. These systems improve efficiency, comfort, ergonomics, accessibility, and user satisfaction of the electronic devices and their supports.

Abstract: Described herein is a multi-user retail photo kiosk system that includes multiple touch screen and Graphic User Interface (GUI) controlled consumer photo editing, photo print and product selection, and photo order placement terminals and multiple photo printers. The user photo kiosk terminals can receive images. Billing and payment is accomplished using barcoded receipts provided at the user terminal for payments for purchased photo products. A printer array incorporating various printers capable of producing prints or various sizes and formats can be configured as a horizontal counter or as a vertical tower and includes means to alert the user that their photo print order is complete. In addition, the system automatically notifies operators if equipment service, maintenance, media refilling, and/or post printing finishing procedures are required.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: Support systems and stands for electronic devices include tilt hinges, lift arms, and their component parts. Some tilt hinges include assemblies for guiding and retaining bars or protrusions into preferred positioning within receiver openings to unify the parts, particularly as they move, and to reduce wobble or slop in the joints. Lift arms provide simplified and low-cost guidance and counterbalance mechanisms for controlling movement of the electronic device relative to the base of a stand. In some cases, the lift arms have sheaths to help protect or cover mechanisms while allowing additional space for the mechanisms within the lift arm. Other interconnection systems hide and protect a connector interface between the stand and the electronic device within a housing until unlocked and the connector is moved into an exposed position. These systems improve efficiency, comfort, ergonomics, accessibility, and user satisfaction of the electronic devices and their supports.

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.

Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations.

Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.

Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.

Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.

Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.

Abstract: Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.