Abstract: A method and device for injecting a liquid sample into an electrolyte channel in a microfluidics device is disclosed. The device has a channel network that includes an electrolyte channel having upstream and downstream channel portions and first, second, and third side channels that intersect the electrolyte channel between the two channel portions at first, second, and third ports, respectively. In the method, a sample is moved electrokinetically into the electrolyte channel, to form a defined sample volume therein. By simultaneously controlling the voltage applied to the three side channels, and at least one of the upstream and downstream channel end portions, the sample volume element can be shaped to have a desired leading- and trailing-edge shape and/or distribution of sample components within the volume elements.

Abstract: A fully integrated monolithic small volume PCR-CE device in glass, or the like materials, is fabricated using thin film metal heaters and thermocouples to thermally cycle sub-microliter PCR volumes. Successful amplification of a PCR fragment is demonstrated on a PCR-CE chip. The process utilizes a linear polyacrylamide surface coating coupled with addition of BSA to the amplification buffer was necessary to obtain amplification efficiencies comparable to a positive control. The micro-reactor reduced significantly the time required for amplification and the reaction volume was in the sub-microlitre regime. Likewise addressed are the known problems connected with reliable microfabrication of metal coatings and the insulating layers required to shield these layers from the PCR reaction mix, and the longstanding unresolved issue of exposed metal regions in the PCR-CE chip resulting in electrolysis of water and bubble formation whenever a voltage is applied.

Abstract: There is provided a method and apparatus for the prioritization, multiple queuing and selective processing of PVC management frames by a Frame Relay message processing device. The device had an input port for receiving the messages. It also provides a number of message queues for storing and retrieving the received messages, each of the queues respectively corresponding to one of a number of response priority levels which vary from highest priority to lowest priority. Each of the response priority levels is assigned to a number of message classes associated with predetermined link management processes for communicating the status of message relay links among networking devices. The message processing device has a first processor for determining the message class associated with each of the received messages and for allocating each of the messages to a corresponding one of the queues based upon the response priority level assigned to the determined message class.

Abstract: Integrated microfluidic devices comprising at least an enrichment channel and a main electrophoretic flowpath are provided. In the subject integrated devices, the enrichment channel and the main electrophoretic flowpath are positioned so that waste fluid flows away from said main electrophoretic flowpath through a discharge outlet. The subject devices find use in a variety of electrophoretic applications, including clinical assays, high throughput screening for genomics and pharmaceutical applications, point-or-care in vitro diagnostics, molecular genetic analysis and nucleic acid diagnostics, cell separations, and bioresearch generally.

Abstract: A set of building blocks useful for constructing model structures includes a plurality of building blocks comprising block bodies and block interconnecting structure. The block interconnecting structure releasably locks each block to one or more adjacent blocks by resisting the blocks being pulled apart from each other. The interconnecting structure does provide, however, a limited amount of lateral play between the blocks so that the interconnected blocks may be moved laterally with respect to each other. The interconnecting structure preferably comprises one or more connecting elements installed into respective apertures in the block bodies. Some blocks have connecting elements with both an inserting end that projects above an outer surface of the block body and a receiving end disposed within the aperture. Other blocks have connecting elements having only a receiving end.

Abstract: A multiplexing data communication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a T1 line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of the fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).

Abstract: A multiplexing data communication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a T1 line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of a fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).

Abstract: A multiplexing data commmunication system (10) provides for communication between a plurality of microcomputer terminals (12) with a host computer (30). Communications from the microcomputer (12) are multiplexed over a Tl line (26) between two DMI interfaces (22 and 24). The DMI interface (24) includes an adaptive digital network interface (62) which processes the multiplex data in a serial manner allowing for flexibility in framing the data and processing protocol information. Program control in the adaptive digital network interface (62) is performed in part by the status of three counters (266, 268 and 272) and the bit present at the output of a fifo memory (112) allowing for increased processing speeds. Furthermore, processing speed is enhanced through use of an instruction set allowing simultaneous strobing and enabling of the elements of the adaptive digital network interface (62).