Patents by Inventor Stephen Joseph Gaul

Stephen Joseph Gaul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10224351
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: March 5, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Stephen Joseph Gaul
  • Patent number: 10211241
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: February 19, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Stephen Joseph Gaul
  • Publication number: 20150357971
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 10, 2015
    Inventor: Stephen Joseph Gaul
  • Publication number: 20150279876
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Application
    Filed: June 16, 2015
    Publication date: October 1, 2015
    Inventor: Stephen Joseph Gaul
  • Patent number: 9147774
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: September 29, 2015
    Assignee: Intersil Americas LLC
    Inventor: Stephen Joseph Gaul
  • Publication number: 20140007927
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Application
    Filed: September 10, 2013
    Publication date: January 9, 2014
    Applicant: Intersil Americas Inc.
    Inventor: Stephen Joseph Gaul
  • Patent number: 8558103
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: October 15, 2013
    Assignee: Intersil Americas Inc.
    Inventor: Stephen Joseph Gaul
  • Patent number: 8288892
    Abstract: A device which can dynamically configure an array of power supply cells such as photovoltaic (PV) solar cells to provide power to a load device based on the power requirements of the load device. By selectively configuring the array of power supply cells according to one of a number of available series/parallel connection schemes, the supplied power can be more closely tailored by a controller to the requirements of the load device.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 16, 2012
    Assignee: Intersil Americas Inc.
    Inventor: Stephen Joseph Gaul
  • Publication number: 20120248627
    Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.
    Type: Application
    Filed: June 18, 2012
    Publication date: October 4, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Stephen Joseph Gaul, Francois Hebert
  • Patent number: 8268693
    Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: September 18, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Stephen Joseph Gaul, Michael D. Church, Brent R. Doyle
  • Patent number: 8232137
    Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: July 31, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Stephen Joseph Gaul, Francois Hebert
  • Publication number: 20110140126
    Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.
    Type: Application
    Filed: May 4, 2010
    Publication date: June 16, 2011
    Inventors: Stephen Joseph Gaul, Francois Hebert
  • Publication number: 20110115047
    Abstract: Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.
    Type: Application
    Filed: June 4, 2010
    Publication date: May 19, 2011
    Inventors: Francois Hebert, Aaron Gibby, Stephen Joseph Gaul
  • Publication number: 20110101787
    Abstract: A device which can dynamically configure an array of power supply cells such as photovoltaic (PV) solar cells to provide power to a load device based on the power requirements of the load device. By selectively configuring the array of power supply cells according to one of a number of available series/parallel connection schemes, the supplied power can be more closely tailored by a controller to the requirements of the load device.
    Type: Application
    Filed: February 17, 2010
    Publication date: May 5, 2011
    Inventor: Stephen Joseph Gaul
  • Patent number: 7804143
    Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: September 28, 2010
    Assignee: Intersil Americas, Inc.
    Inventors: Stephen Joseph Gaul, Michael D. Church, Brent R. Doyle
  • Publication number: 20100191383
    Abstract: Exemplary embodiments provide an array of solar power generation devices, and method for forming the array. Each solar power generation device can be defined as a cell, a group of cells, a panel subarray, a panel from an array of panels, etc. The solar power generation device can include a controller which can address and control each solar power generation device individually. A test method and fixture is also described, which can be used to program the controller such that incorrect assembly of the array during manufacture is overcome.
    Type: Application
    Filed: January 8, 2010
    Publication date: July 29, 2010
    Applicant: Intersil Americas, Inc.
    Inventor: Stephen Joseph Gaul
  • Publication number: 20100186795
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Application
    Filed: May 21, 2009
    Publication date: July 29, 2010
    Inventor: Stephen Joseph Gaul
  • Publication number: 20100186799
    Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.
    Type: Application
    Filed: May 21, 2009
    Publication date: July 29, 2010
    Inventor: Stephen Joseph Gaul
  • Patent number: 7709907
    Abstract: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: May 4, 2010
    Assignee: Intersil Americas Inc.
    Inventors: Stephen Joseph Gaul, Michael D. Church, James Edwin Vinson
  • Patent number: 6114768
    Abstract: A bonded wafer has a first handle wafer 12, a device layer 10', an interconnect layer 14, and a number of vias filled with conductive material that extends between the surfaces 6, 8 of the device layer 10'. the interconnect layer 14 has conductors that connect internal device contacts to the conductive vias. A second handle wafer 40 of glass is bonded to the interconnect layer 14 and the first handle wafer is removed. Bottom, external contacts 36 are formed on surface 6 of device layer 10'.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: September 5, 2000
    Assignee: Intersil Corporation
    Inventors: Stephen Joseph Gaul, Jose Avelino Delgado