Patents by Inventor Stephen Joseph Gaul
Stephen Joseph Gaul has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224351Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: GrantFiled: August 14, 2015Date of Patent: March 5, 2019Assignee: INTERSIL AMERICAS LLCInventor: Stephen Joseph Gaul
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Patent number: 10211241Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: GrantFiled: June 16, 2015Date of Patent: February 19, 2019Assignee: INTERSIL AMERICAS LLCInventor: Stephen Joseph Gaul
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Publication number: 20150357971Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: ApplicationFiled: August 14, 2015Publication date: December 10, 2015Inventor: Stephen Joseph Gaul
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Publication number: 20150279876Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: ApplicationFiled: June 16, 2015Publication date: October 1, 2015Inventor: Stephen Joseph Gaul
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Patent number: 9147774Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: GrantFiled: September 10, 2013Date of Patent: September 29, 2015Assignee: Intersil Americas LLCInventor: Stephen Joseph Gaul
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Publication number: 20140007927Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: Intersil Americas Inc.Inventor: Stephen Joseph Gaul
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Patent number: 8558103Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: GrantFiled: May 21, 2009Date of Patent: October 15, 2013Assignee: Intersil Americas Inc.Inventor: Stephen Joseph Gaul
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Patent number: 8288892Abstract: A device which can dynamically configure an array of power supply cells such as photovoltaic (PV) solar cells to provide power to a load device based on the power requirements of the load device. By selectively configuring the array of power supply cells according to one of a number of available series/parallel connection schemes, the supplied power can be more closely tailored by a controller to the requirements of the load device.Type: GrantFiled: February 17, 2010Date of Patent: October 16, 2012Assignee: Intersil Americas Inc.Inventor: Stephen Joseph Gaul
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Publication number: 20120248627Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.Type: ApplicationFiled: June 18, 2012Publication date: October 4, 2012Applicant: INTERSIL AMERICAS INC.Inventors: Stephen Joseph Gaul, Francois Hebert
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Patent number: 8268693Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.Type: GrantFiled: August 25, 2010Date of Patent: September 18, 2012Assignee: Intersil Americas Inc.Inventors: Stephen Joseph Gaul, Michael D. Church, Brent R. Doyle
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Patent number: 8232137Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.Type: GrantFiled: May 4, 2010Date of Patent: July 31, 2012Assignee: Intersil Americas Inc.Inventors: Stephen Joseph Gaul, Francois Hebert
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Publication number: 20110140126Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.Type: ApplicationFiled: May 4, 2010Publication date: June 16, 2011Inventors: Stephen Joseph Gaul, Francois Hebert
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Publication number: 20110115047Abstract: Methods and structures for a semiconductor device can use mask openings of varying widths to form structures of different depths, different materials, and different functionality. For example, processes and structures for forming shallow trench isolation, deep isolation, trench capacitors, base, emitter, and collector, among other structures for a lateral bipolar transistor are described.Type: ApplicationFiled: June 4, 2010Publication date: May 19, 2011Inventors: Francois Hebert, Aaron Gibby, Stephen Joseph Gaul
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Publication number: 20110101787Abstract: A device which can dynamically configure an array of power supply cells such as photovoltaic (PV) solar cells to provide power to a load device based on the power requirements of the load device. By selectively configuring the array of power supply cells according to one of a number of available series/parallel connection schemes, the supplied power can be more closely tailored by a controller to the requirements of the load device.Type: ApplicationFiled: February 17, 2010Publication date: May 5, 2011Inventor: Stephen Joseph Gaul
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Patent number: 7804143Abstract: A “tabbed” MOS device provides radiation hardness while supporting reduced gate width requirements. The “tabbed” MOS device also utilizes a body tie ring, which reduces field threshold leakage. In one implementation the “tabbed” MOS device is designed such that a width of the tab is based on at least a channel length of the MOS device such that a radiation-induced parasitic conduction path between the source and drain region of the device has a resistance that is higher than the device channel resistance.Type: GrantFiled: February 18, 2009Date of Patent: September 28, 2010Assignee: Intersil Americas, Inc.Inventors: Stephen Joseph Gaul, Michael D. Church, Brent R. Doyle
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Publication number: 20100191383Abstract: Exemplary embodiments provide an array of solar power generation devices, and method for forming the array. Each solar power generation device can be defined as a cell, a group of cells, a panel subarray, a panel from an array of panels, etc. The solar power generation device can include a controller which can address and control each solar power generation device individually. A test method and fixture is also described, which can be used to program the controller such that incorrect assembly of the array during manufacture is overcome.Type: ApplicationFiled: January 8, 2010Publication date: July 29, 2010Applicant: Intersil Americas, Inc.Inventor: Stephen Joseph Gaul
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Publication number: 20100186795Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel. The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: ApplicationFiled: May 21, 2009Publication date: July 29, 2010Inventor: Stephen Joseph Gaul
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Publication number: 20100186799Abstract: Exemplary embodiments provide a solar cell device, and method for forming the solar cell device by integrating a switch component into a solar cell element. The solar cell element can include a solar cell, a solar cell array and/or a solar cell panel The integrated solar cell element can be used for a solar sensor, while the solar sensor can also use discrete switches for each solar cell area of the sensor. Exemplary embodiments also provide a connection system for the solar cell elements and a method for super-connecting the solar cell elements to provide a desired connection path or a desired power output through switch settings. The disclosed connection systems and methods can allow for by-passing underperforming solar cell elements from a plurality of solar cell elements. In embodiments, the solar cell element can be extended to include a battery or a capacitor.Type: ApplicationFiled: May 21, 2009Publication date: July 29, 2010Inventor: Stephen Joseph Gaul
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Patent number: 7709907Abstract: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region.Type: GrantFiled: November 7, 2005Date of Patent: May 4, 2010Assignee: Intersil Americas Inc.Inventors: Stephen Joseph Gaul, Michael D. Church, James Edwin Vinson
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Patent number: 6114768Abstract: A bonded wafer has a first handle wafer 12, a device layer 10', an interconnect layer 14, and a number of vias filled with conductive material that extends between the surfaces 6, 8 of the device layer 10'. the interconnect layer 14 has conductors that connect internal device contacts to the conductive vias. A second handle wafer 40 of glass is bonded to the interconnect layer 14 and the first handle wafer is removed. Bottom, external contacts 36 are formed on surface 6 of device layer 10'.Type: GrantFiled: July 7, 1998Date of Patent: September 5, 2000Assignee: Intersil CorporationInventors: Stephen Joseph Gaul, Jose Avelino Delgado