Patents by Inventor Stephen M. Cea

Stephen M. Cea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190355811
    Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 21, 2019
    Applicant: INTEL CORPORATION
    Inventors: Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Tahir Ghani, Stephen M. Cea, William Hsu, SZUYA S. LIAO, PRATIK A. PATEL
  • Patent number: 10483385
    Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 19, 2019
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
  • Publication number: 20190341384
    Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.
    Type: Application
    Filed: March 15, 2017
    Publication date: November 7, 2019
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea, Rishabh Mehandru
  • Patent number: 10468489
    Abstract: Techniques and mechanisms to provide insulation for a component of an integrated circuit device. In an embodiment, structures of a circuit component are formed in or on a first side of a semiconductor substrate, the structures including a first doped region, a second doped region and a third region between the first doped region and the second doped region. The substrate has formed therein an insulation structure, proximate to the circuit component structures, which is laterally constrained to extend only partially from a location under the circuit component toward an edge of the substrate. In another embodiment, a second side of the substrate—opposite the first side—is exposed by thinning to form the substrate from a wafer. Such thinning enables subsequent back side processing to form a recess in the second side, and to deposit the insulation structure in the recess.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Uygar E. Avci, David L. Kencke, Patrick Morrow, Kerryann Foley, Stephen M. Cea, Rishabh Mehandru
  • Publication number: 20190326290
    Abstract: Techniques are disclosed for forming dual-strain fins for co-integrated n-MOS and p-MOS devices. The techniques can be used to monolithically form tensile-strained fins to be used for n-MOS devices and compressive-strained fins to be used for p-MOS devices utilizing the same substrate, such that a single integrated circuit (IC) can include both of the devices. In some instances, the oppositely stressed fins may be achieved by employing a relaxed SiGe (rSiGe) layer from which the tensile and compressive-strained material can be formed. In some instances, the techniques include the formation of tensile-stressed Si and/or SiGe fins and compressive-stressed SiGe and/or Ge fins using a single relaxed SiGe layer to enable the co-integration of n-MOS and p-MOS devices, where each set of devices includes preferred materials and preferred stress/strain to enhance their respective performance. In some cases, improvements of at least 25% in drive current can be obtained.
    Type: Application
    Filed: December 29, 2016
    Publication date: October 24, 2019
    Applicant: INTEL CORPORATION
    Inventors: STEPHEN M. CEA, RISHABH MEHANDRU, ANUPAMA BOWONDER, ANAND S. MURTHY, TAHIR GHANI
  • Patent number: 10453967
    Abstract: Semiconductor nanowire devices having cavity spacers and methods of fabricating cavity spacers for semiconductor nanowire devices are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires including a discrete channel region. A common gate electrode stack surrounds each of the discrete channel regions of the plurality of vertically stacked nanowires. A pair of dielectric spacers is on either side of the common gate electrode stack, each of the pair of dielectric spacers including a continuous material disposed along a sidewall of the common gate electrode and surrounding a discrete portion of each of the vertically stacked nanowires. A pair of source and drain regions is on either side of the pair of dielectric spacers.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Szuya S. Liao, Stephen M. Cea
  • Patent number: 10411090
    Abstract: Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Rishabh Mehandru, Stephen M. Cea
  • Patent number: 10403752
    Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and lll-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Chandra S. Mohapatra, Anand S. Murthy, Stephen M. Cea, Tahir Ghani
  • Publication number: 20190252525
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Rishabh MEHANDRU, Patrick MORROW, Ranjith KUMAR, Cory E. WEBER, Seiyon KIM, Stephen M. CEA, Tahir GHANI
  • Publication number: 20190221577
    Abstract: An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polyconductive material.
    Type: Application
    Filed: September 30, 2016
    Publication date: July 18, 2019
    Inventors: Aaron D. LILAK, Patrick THEOFANIS, Patrick MORROW, Rishabh MEHANDRU, Stephen M. CEA
  • Publication number: 20190189464
    Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 20, 2019
    Inventors: Aaron D. Lilak, Harold W. Kennel, Patrick Morrow, Rishabh Mehandru, Stephen M. Cea
  • Publication number: 20190172950
    Abstract: An integrated circuit apparatus including a body; a transistor formed on a first portion of the body, the transistor including a gate stack and a channel defined in the body between a source and a drain; and a plug formed in a second portion of the body, the plug including a material operable to impart a stress on the first portion of the body. A method of forming an integrated circuit device including forming a transistor body on a substrate; forming a transistor device in a first portion of the transistor body on a first side of the substrate; and dividing the transistor body into at least the first portion and a second portion with a plug in the transistor body, the plug including a material operable to impart a stress on the first portion of the body, wherein the material is introduced through a second side of the substrate.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 6, 2019
    Inventors: Aaron D. LILAK, Sean T. MA, Rishabh MEHANDRU, Patrick MORROW, Stephen M. CEA
  • Patent number: 10304929
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Patent number: 10304946
    Abstract: Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure includes a semiconductor fin separated vertically into an upper region and a lower region. A first plurality of gate structures is included for controlling the upper region of the semiconductor fin. A second plurality of gate structures is included for controlling the lower region of the semiconductor fin. The second plurality of gate structures has a conductivity type opposite the conductivity type of the first plurality of gate structures.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Ranjith Kumar, Cory E. Weber, Seiyon Kim, Stephen M. Cea, Tahir Ghani
  • Publication number: 20190115466
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Applicant: INTEL CORPORATION
    Inventors: STEPHEN M. CEA, ROZA KOTLYAR, HAROLD W. KENNEL, GLENN A. GLASS, ANAND S. MURTHY, WILLY RACHMADY, TAHIR GHANI
  • Publication number: 20190035893
    Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
    Type: Application
    Filed: October 1, 2018
    Publication date: January 31, 2019
    Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Anand S. Murthy, Glenn A. Glass, Kelin J. Kuhn, Tahir Ghani
  • Publication number: 20190027503
    Abstract: Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.
    Type: Application
    Filed: September 25, 2015
    Publication date: January 24, 2019
    Inventors: Aaron D. LILAK, Patrick MORROW, Stephen M. CEA, Rishabh MEHANDRU, Cory E. WEBER
  • Patent number: 10153372
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 11, 2018
    Assignee: INTEL CORPORATION
    Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady, Tahir Ghani
  • Publication number: 20180331183
    Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 17, 2015
    Publication date: November 15, 2018
    Inventors: AARON D. LILAK, RISHABH MEHANDRU, HAROLD W. KENNEL, PAUL B. FISCHER, STEPHEN M. CEA
  • Publication number: 20180323195
    Abstract: Disclosed herein are stacked channel structures for metal oxide semiconductor field effect transistors (MOSFETs) and related circuit elements, computing devices, and methods. For example, a stacked channel structure may include: a semiconductor substrate having a substrate lattice constant; a fin extending away from the semiconductor substrate, the fin having an upper region and a lower region; a first transistor in the lower region, wherein the first transistor has a first channel, the first channel has a first lattice constant, and the first lattice constant is different from the substrate lattice constant; and a second transistor in the upper region, wherein the second transistor has a second channel, the second channel has a second lattice constant, and the second lattice constant is different from the substrate lattice constant.
    Type: Application
    Filed: December 3, 2015
    Publication date: November 8, 2018
    Applicant: Intel Corporation
    Inventors: Rishabh Mehandru, Roza Kotlyar, Stephen M. Cea, Patrick H. Keys