Abstract: A method is provided for allowing the transmission of digital video segments along a number of transmission channels, with the line speed, or rate of transmission in bits per second, being variable during a transmission. For each transmission channel, video data segments are stored in a data buffer, along with data segments known as Write Control Blocks (WCBs). Each WCB includes a pointer to the video data segment with which it is associated and a line speed code indicating the preferred rate of data transmission. The addresses of the WCBs are stored in a FIFO buffer which is established for each transmission channel. When coded information within a WCB indicates that a speed change is needed, a run-time subroutine executing in a co-processor sets bits within a channel control word forming a portion of each WCB to stop a DMA process and to issue an interrupt when the corresponding video segment is to be transmitted.

Abstract: A method and apparatus for communicating between two, or more, devices receiving a variable-length bit stream. The method and apparatus allocate an input buffer larger than any read size selected for the receiving unit and the reception stops when the input buffer is full.

Abstract: A method for communicating between two, or more, devices comprises the steps of (1) allocating, in a receiving device, a plurality of input buffers linked in a circular queue for continuous reading of data; (2) setting up a timer for determining the end of received data streams; (3) receiving a variable-length bit stream comprising data; synchronization of data; (5) determining whether data is being received upon expiration of the timer; (6) resynchronizing for a subsequent bit stream if not receiving data in step (5); (7) checking one of the plurality of input buffers for idle patterns if data is being received in step (5); (8) restarting the timer and returning to step (4), when idle patterns are not detected in step (7); and (9) disabling the receiver and resynchronizing and returning to step (4), when idle patterns are received in step (7).