Patents by Inventor Stephen P. DeOrnellas
Stephen P. DeOrnellas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080318432Abstract: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.Type: ApplicationFiled: September 2, 2008Publication date: December 25, 2008Applicant: TEGAL CORPORATIONInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Kurt A. Olson
-
Patent number: 7223699Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: March 23, 2005Date of Patent: May 29, 2007Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C Vail, Kurt A. Olson
-
Patent number: 6958295Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.Type: GrantFiled: October 19, 2000Date of Patent: October 25, 2005Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer
-
Patent number: 6951820Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.Type: GrantFiled: November 9, 2001Date of Patent: October 4, 2005Assignee: Silicon Valley BankInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer
-
Patent number: 6905969Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: May 28, 2002Date of Patent: June 14, 2005Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Patent number: 6774046Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.Type: GrantFiled: June 13, 2001Date of Patent: August 10, 2004Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Alferd Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora
-
Patent number: 6620335Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: December 7, 1999Date of Patent: September 16, 2003Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Patent number: 6521081Abstract: A rotary transformer includes a resonant circuit and a coil drive circuit. The resonant circuit includes a resonating capacitor connected to a power MOS transistor, coupled across the primary coil of the transformer. The coil drive circuit includes a diode connected to a power MOS transistor coupled across the primary coil of the transformer. A microprocessor detects changes in the voltage across the primary coil. The resonant circuit is connected and disconnected from the transformer during a power transfer mode and a data transfer mode, respectively. During the power transfer mode, stored energy in the leakage inductance of the primary coil is used for power coupling, via the resonant circuit, instead of being dissipated as heat. The resonant circuit is disconnected from the rotary transformer during the data transfer mode to maximize bandwidth for two-way data transfer between the primary and secondary sides of the transformer.Type: GrantFiled: June 14, 2001Date of Patent: February 18, 2003Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
-
Patent number: 6500314Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: July 3, 1996Date of Patent: December 31, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Patent number: 6492280Abstract: A method and apparatus provide for etching a semiconductor wafer using a two step physical etching and a chemical etching process in order to create vertical sidewalls required for high density DRAMs and FRAMs.Type: GrantFiled: March 2, 2000Date of Patent: December 10, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Alferd Cofer, Paritosh Rajora
-
Patent number: 6486069Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.Type: GrantFiled: December 3, 1999Date of Patent: November 26, 2002Assignee: Tegal CorporationInventors: Steven Marks, Leslie G. Jerde, Stephen P. DeOrnellas
-
Publication number: 20020139665Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: ApplicationFiled: May 28, 2002Publication date: October 3, 2002Applicant: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Publication number: 20020132485Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.Type: ApplicationFiled: November 9, 2001Publication date: September 19, 2002Applicant: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer
-
Patent number: 6410448Abstract: A plasma etch reactor 20 includes a reactor chamber 22 with a grounded upper electrode 24, a lower electrode 28 which is attached to a high frequency power supply 30 and a low frequency power supply 32, and a peripheral electrode 26 which is located between the upper and lower electrode, and which is allowed to have a floating potential. Rare earth magnets 46, 47 are used to establish the magnetic field which confines the plasma developed within the reactor chamber 22. The plasma etch reactor 20 is capable of etching emerging films used with high density semiconductor devices.Type: GrantFiled: August 27, 1999Date of Patent: June 25, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Alferd Cofer, Robert C. Vail
-
Patent number: 6391148Abstract: Method and apparatus for etching a silicide stack including etching the silicide layer at a temperature elevated from that used to etch the rest of the layers in order to accomplish anisotropic etch.Type: GrantFiled: January 12, 2001Date of Patent: May 21, 2002Assignee: Tegal CorporationInventors: Steven Marks, Leslie G. Jerde, Stephen P. DeOrnellas
-
Patent number: 6360686Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.Type: GrantFiled: August 24, 1999Date of Patent: March 26, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
-
Patent number: 6354240Abstract: A plasma etch reactor 20 includes a upper electrode 24, a lower electrode 24, a peripheral ring electrode 26 disposed therebetween. The upper electrode 24 is grounded, the peripheral electrode 26 is powered by a high frequency AC power supply, while the lower electrode 28 is powered by a low frequency AC power supply, as well as a DC power supply. The reactor chamber 22 is configured with a solid source 50 of gaseous species and a protruding baffle 40. A nozzle 36 provides a jet stream of process gases in order to ensure uniformity of the process gases at the surface of a semiconductor wafer 48. The configuration of the plasma etch reactor 20 enhances the range of densities for the plasma in the reactor 20, which range can be selected by adjusting more of the power supplies 30, 32.Type: GrantFiled: September 11, 1998Date of Patent: March 12, 2002Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer, Robert C. Vail, Kurt A. Olson
-
Publication number: 20010031561Abstract: A method for minimizing the critical dimension growth of a feature on a semiconductor wafer includes performing an etch operation in a reactor 20 and controlling the temperature of the wafer 26 by controlling the pressure of the gas contacting the backside of the wafer 26 and/or providing a heat source 56 such as for example in the chuck 46 or electrode 28 associated with the wafer 26 in order to heat the wafer 26.Type: ApplicationFiled: June 13, 2001Publication date: October 18, 2001Applicant: Tegal CorporationInventors: Stephen P. DeOrnellas, Alferd Cofer, Leslie G. Jerde, Kurt A. Olson, Paritosh Rajora
-
Publication number: 20010029894Abstract: A reactor 20 includes a shield 50 which prevents the deposition of materials along a line-of-sight path from a wafer 26 toward and onto an electrode 32, or a window 38 which couples an electrode 32 to a reaction chamber of the reactor 20. The shield can be comprised of a conductor and/or an insulator. The shield can affect the character of a plasma generated in the reactor.Type: ApplicationFiled: June 14, 2001Publication date: October 18, 2001Applicant: Tegal CorporationInventors: Stephen P. DeOrnellas, Robert A. Ditizio
-
Patent number: 6287975Abstract: A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.Type: GrantFiled: January 20, 1998Date of Patent: September 11, 2001Assignee: Tegal CorporationInventors: Stephen P. DeOrnellas, Leslie G. Jerde, Alferd Cofer