Patents by Inventor Stephen P. Sample
Stephen P. Sample has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7739097Abstract: A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.Type: GrantFiled: April 22, 2002Date of Patent: June 15, 2010Assignee: Quickturn Design Systems Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Patent number: 6882176Abstract: A programmable logic device architecture. This programmable logic architecture includes a first logic block (425) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (415), which interfaces with the first logic block (425), for performing JTAG functions, configuring the first logic block (425), initializing the first logic block (425), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block (425) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (511). The first logic block (425) includes a plurality of second logic blocks (505) which may be programmably coupled using a second programmable interconnect network (521). The second programmable interconnect network (521) may be programmably coupled to the first programmable interconnect network (511).Type: GrantFiled: March 7, 2003Date of Patent: April 19, 2005Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Kevin A. Norman, Rakesh H. Patel, Stephen P. Sample, Michael R. Butts
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Patent number: 6842729Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.Type: GrantFiled: March 26, 2002Date of Patent: January 11, 2005Assignee: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. D'Amour, Thomas S. Payne
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Patent number: 6732068Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: GrantFiled: August 2, 2001Date of Patent: May 4, 2004Assignee: Quickturn Design Systems Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Patent number: 6694464Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common input/output pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system. A method for dynamically testing the interconnect between integrated circuits is also disclosed.Type: GrantFiled: October 23, 2000Date of Patent: February 17, 2004Assignee: Quickturn Design Systems, Inc.Inventors: Barton L. Quayle, Stephen P. Sample
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Patent number: 6625793Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic.Type: GrantFiled: September 6, 2001Date of Patent: September 23, 2003Assignee: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts
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Patent number: 6570404Abstract: A programmable logic device architecture. This programmable logic architecture includes a first logic block (425) containing programmable logic elements for performing logic functions. The architecture may also include a diagnostic block interface (415), which interfaces with the first logic block (425), for performing JTAG functions, configuring the first logic block (425), initializing the first logic block (425), interfacing with off-chip diagnostic and test devices and equipment, and performing other similar functions. The first logic block (425) may be programmably coupled to other components on the integrated circuit using a first programmable interconnect network (511). The first logic block (425) includes a plurality of second logic blocks (505) which may be programmably coupled using a second programmable interconnect network (521). The second programmable interconnect network (521) may be programmably coupled to the first programmable interconnect network (511).Type: GrantFiled: March 26, 1997Date of Patent: May 27, 2003Assignee: Altera CorporationInventors: Kevin A. Norman, Rakesh H. Patel, Stephen P. Sample, Michael R. Butts
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Patent number: 6567967Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.Type: GrantFiled: June 4, 2001Date of Patent: May 20, 2003Assignee: Monterey Design Systems, Inc.Inventors: Yaacov I. Greidinger, David S. Reed, Ara Markosian, Stephen P. Sample, Jonathan A. Frankle, Hasmik Lazaryan
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Publication number: 20030074178Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: ApplicationFiled: April 22, 2002Publication date: April 17, 2003Applicant: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Publication number: 20020177990Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: ApplicationFiled: September 4, 2001Publication date: November 28, 2002Inventor: Stephen P. Sample
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Publication number: 20020161568Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: ApplicationFiled: August 2, 2001Publication date: October 31, 2002Applicant: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Publication number: 20020107682Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.Type: ApplicationFiled: March 26, 2002Publication date: August 8, 2002Applicant: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. D'Amour, Thomas S. Payne
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Publication number: 20020095649Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect.Type: ApplicationFiled: September 6, 2001Publication date: July 18, 2002Applicant: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts
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Publication number: 20020087940Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.Type: ApplicationFiled: June 4, 2001Publication date: July 4, 2002Inventors: Yaacov I. Greidinger, David S. Reed, Ara Markosian, Stephen P. Sample, Jonathan A. Frankle, Hasmik Lazaryan
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Publication number: 20020087939Abstract: An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.Type: ApplicationFiled: May 25, 2001Publication date: July 4, 2002Inventors: Yaacov I. Greidinger, David S. Reed, Ara Markosian, Stephen P. Sample, Jonathan A. Frankle, Hasmik Lazaryan
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Patent number: 6377911Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. A network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.Type: GrantFiled: July 12, 1999Date of Patent: April 23, 2002Assignee: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. D'Amour, Thomas S. Payne
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Patent number: 6377912Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.Type: GrantFiled: August 13, 1999Date of Patent: April 23, 2002Assignee: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Mikhail Bershteyn, Michael R. Butts, Jerry R. Bauer
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Patent number: 6353552Abstract: Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory block is coupled to the logic element. The memory block includes a memory storage cell to store a first data bit, a shadow cell to store a second data bit, and a transfer circuit. When a first control line of a transfer circuit is asserted, the second bit is transferred from the shadow cell to the memory storage cell. When a second control line of the transfer circuit is asserted, the first bit is transferred from the memory storage cell to the shadow cell.Type: GrantFiled: March 26, 2001Date of Patent: March 5, 2002Assignees: Altera Corporation, Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel, Chao Chiang Chen
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Patent number: 6317367Abstract: An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured with a width and depth that is independent and separate from the width and depth of the other ports. The memory also includes a port for taking a synchronous snapshot of the contents of the memory or for loading the memory to an initial state. The memory shares routing lines used by a low level logic element thereby alleviating the need to add routing lines to an interconnect network just to satisfy the memory requirements.Type: GrantFiled: December 21, 2000Date of Patent: November 13, 2001Assignees: Altera Corporation, Quickturn Design SystemsInventors: Stephen P. Sample, Michael R. Butts, Kevin A. Norman, Rakesh H. Patel, Chao Chiang Chen
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Patent number: 6289494Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect.Type: GrantFiled: November 12, 1997Date of Patent: September 11, 2001Assignee: Quickturn Design Systems, Inc.Inventors: Stephen P. Sample, Michael R. Butts