Abstract: The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.

Abstract: A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk. An apparatus is provided that includes a load-store unit to maintain execution operations. The load-store unit includes a tablewalker to perform a tablewalk and includes an input indicative of the operation being speculative or non-speculative as well as a state machine to determine actions performed during the tablewalk based on the input. The apparatus also includes a translation look-aside buffer. Computer readable storage devices for performing the methods and adapting a fabrication facility to manufacture the apparatus are provided.

Abstract: The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.

Abstract: The present application describes a method and apparatus for filtering requests to a translation lookaside buffer (TLB). Some embodiments of the method include receiving, from a first translation lookaside buffer (TLB), an indication of a first virtual address associated with a request to a second TLB for a page table entry in response to a miss in the first TLB. Some embodiments of the method also include filtering the request based on a comparison of the first virtual address and one or more second virtual addresses associated with one or more previous requests to the second TLB.

Abstract: The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from a memory into one or more caches by comparing a first address of a memory access request to addresses in an address window that includes one or more previously fetched addresses and one or more addresses to be fetched.

Abstract: The present application describes a method and apparatus for filtering requests to a translation lookaside buffer (TLB). Some embodiments of the method include receiving, from a first translation lookaside buffer (TLB), an indication of a first virtual address associated with a request to a second TLB for a page table entry in response to a miss in the first TLB. Some embodiments of the method also include filtering the request based on a comparison of the first virtual address and one or more second virtual addresses associated with one or more previous requests to the second TLB.

Abstract: A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk. An apparatus is provided that includes a load-store unit to maintain execution operations. The load-store unit includes a tablewalker to perform a tablewalk and includes an input indicative of the operation being speculative or non-speculative as well as a state machine to determine actions performed during the tablewalk based on the input. The apparatus also includes a translation look-aside buffer. Computer readable storage devices for performing the methods and adapting a fabrication facility to manufacture the apparatus are provided.

Abstract: The present invention provides a method and apparatus for using prefetch hints. One embodiment of the method includes bypassing, at a first prefetcher associated with a first cache, issuing requests to prefetch data from a number of memory addresses in a sequence of memory addresses determined by the first prefetcher. The number is indicated in a request received from a second prefetcher associated with a second cache. This embodiment of the method also includes issuing, from the first prefetcher, a request to prefetch data from a memory address subsequent to the bypassed memory addresses.

Abstract: The present invention provides a method and apparatus for throttling prefetch requests for a cache. One embodiment of the method includes selecting a sequence of relative addresses for prefetching data from a memory into lines of a cache in response to detecting a cache miss to a first address. The sequence of relative addresses is determined relative to the first address. This embodiment of the method also includes issuing a prefetch request for data from a memory address indicated by one of the sequence of relative addresses when at least one previous prefetch stream accessed prefetched data associated with this one of the sequence of relative addresses.

Abstract: A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue.

Abstract: A method and apparatus are provided for controlling a translation lookaside buffer in connection with the execution of an atomic instruction. The method comprises identifying load instructions within a plurality of instructions to be executed, and placing the identified load instructions in a queue prior to execution. An atomic instruction identified in the queue is prevented from executing until the atomic instruction is the oldest instruction in the queue. The apparatus comprises a queue and a translation lookaside buffer. The queue is adapted to: identify an atomic instruction within a plurality of instructions to be executed; prevent execution of the atomic instruction until it is the oldest instruction in the queue; and send a virtual address corresponding to the atomic instruction and an atomic load signal in response to determining that the atomic instruction is the oldest instruction in the queue.

Abstract: A two-level replacement scheme is provided for selecting an entry in a cache memory to replace when a cache miss takes place and the memory is full. The scheme divides the tags associated with each memory location of the cache into two or more groups, each group relating to a subset of memory locations of the cache. The scheme uses a first algorithm to select one of the groups and passes the tags for the group through a second algorithm. The second algorithm produces a local index which, when combined with a group index, produces a replacement index that identifies a memory location in the cache to replace.

Abstract: The present invention provides a method and apparatus for adapting aggressiveness of a pre-fetcher in a processor-based system. One embodiment includes modifying a rate for pre-fetching data from a memory into one or more caches by comparing a first address of a memory access request to addresses in an address window that includes one or more previously fetched addresses and one or more addresses to be fetched.

Abstract: Instructions involving a relatively significant data transfer or a particular type of data transfer via a cache result in the application of a restricted access policy to control access to one or more partitions of the cache so as to reduce or prevent the overwriting of data that is expected to be subsequently used by the cache or by a processor. A processor or other system component may assert a signal which is utilized to select between one or more access policies and the selected access policy then may be applied to control access to one or more ways of the cache during the data transfer operation associated with the instruction. The access policy typically represents an access restriction to particular cache partitions, such as a restriction to one or more particular cache ways or one or more particular cache lines.

Abstract: A cache read request is received at a cache comprising a plurality of data arrays, each of the data arrays comprising a plurality of ways. Cache line data from each most recently used way of each of the plurality of data arrays is selected in response to the cache read request and selecting a first data of the received cache line data from the most recently used way of the cache. An execution of an instruction is stalled if data identified by the cache read request is not present in the cache line data from the most recently used way of the cache. A second data from a most recently used way of one of the plurality of data arrays other than the most recently used data array is selected as comprising data identified by the cache read request. The second data is provided for use during the execution of the instruction.

Abstract: Instructions involving a relatively significant information transfer or a particular type of information transfer via a cache, or specified address ranges within cache causing a cache miss result in the application of a restricted access policy to control access to one or more partitions of the cache so as to reduce or prevent the overwriting of information that is expected to be subsequently used by the cache or by a processor. A processor or other system component may assert a signal which is utilized to select between one or more access policies based on instructions or their type so that an access may be applied to control access to one or more ways of the cache during the information transfer operation associated with the instruction. Similarly, a cache way select module may select between one or more access policies based on an address range so that an access policy may be applied to control access to one or more ways of the cache during access to a specific range of memory.

Abstract: A full screen of video data is stored in a video memory. A small block of video data to be imminently displayed on a raster scan display device is copied, two double-words (32 bits) at a time, from the video memory to a 6 by 32-bit first in, first out buffer (FIFO). A fill detection circuit determines when the fill level of the FIFO is at or above certain predetermined levels; specifically, 3, 5 and 6 double-words. The current operating mode is stored in a programmable mode register wherein each mode corresponds to a unique screen resolution. For example, one mode corresponds to a 1024 by 768 pixel resolution having 256 colors per pixel, while another mode corresponds to a 320 by 200 pixel resolution having 4 colors per pixel. A minimum fill level is selected by a level selection circuit depending on the current operating mode. Since the FIFO is emptied quickly in a high resolution mode, a higher minimum fill level is selected for high resolution modes than for low resolution modes.

Abstract: A system for horizontal expansion of low resolution display modes onto high resolution displays including flat panels at a variable scaling factor is disclosed. The system may be combined with known methods for vertical expansion to allow low resolution display modes to be expanded onto any high resolution display. Two different methods are provided, one for graphics modes and one for text modes, to attain better screen image quality. In the first method, a first pixel data sequence to be expanded is first oversampled at a multiple of the frequency thereof to produce an intermediate oversampled data sequence. The oversampled data sequence is linearly decimated by a factor of less than unity to produce a replicated second data sequence longer than the first, which is then displayed.

Abstract: A method and system for increasing efficiency in the display of characters on a display within a data processing system, wherein the data processing system includes a system memory and a graphics adapter, the system memory having a page mode. A plurality of characters are stored in the system memory as a plurality of glyph bitmaps. Each character has a width, and each glyph bitmap for a character is arranged as a plurality of scanlines such that each of the scanlines includes the width of the character. Selected glyph bitmaps are transmitted from the system memory to the graphics adapter, wherein an occurrence of breaks in the page mode are minimized when the selected glyph bitmaps are moved from the system memory to the graphics adapter, increasing efficiency in displaying characters on a display.

Abstract: Method and apparatus for enabling an XGA display adapter selectively to support VGA graphics mode virtualization during native mode operation of the adapter by rendering VGA graphics assist hardware and certain VGA registers accessible. In a preferred embodiment, the invention comprises an XGA display adapter which includes a host interface for interfacing the display adapter with a central processing unit (CPU) of a personal computer (PC), VGA graphics assist hardware for performing VGA graphics assist functions, a memory controller for reading and writing a video memory of the PC as requested by the CPU during video memory accesses, and a display interface for generating control and timing signals to a display of the PC. The XGA display adapter also includes a XGA Operating Mode Register having three control bits which can be written by applications software selectively to enable or disable the virtual VGA function of the present invention.