Abstract: Method and apparatus for enabling an XGA display adapter selectively to support VGA graphics mode virtualization during native mode operation of the adapter by rendering VGA graphics assist hardware and certain VGA registers accessible. In a preferred embodiment, the invention comprises an XGA display adapter which includes a host interface for interfacing the display adapter with a central processing unit (CPU) of a personal computer (PC), VGA graphics assist hardware for performing VGA graphics assist functions, a memory controller for reading and writing a video memory of the PC as requested by the CPU during video memory accesses, and a display interface for generating control and timing signals to a display of the PC. The XGA display adapter also includes a XGA Operating Mode Register having three control bits which can be written by applications software selectively to enable or disable the virtual VGA function of the present invention.

Abstract: A method and system for controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least one input/output device having a coprocessor incorporated therein. The system bus electrically connects the system devices. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. Each of the at least one input/output device incorporates control logic therein for (i) monitoring bus activity to calculate the bus mastering time during which the memory controller and the at least one input/output device control the bus, and (ii) outputting an inhibit signal which denies access to the bus by the at least one input/output device if the calculated bus mastering time is equal to or greater than a predetermined bus mastering time period.

Abstract: A method and system for monitoring and controlling access to a system bus in a computer system is provided. The system devices include a central processing unit, a memory controller for controlling access to system memory, and at least first and second input/output devices each having a coprocessor incorporated therein. The system bus electrically interconnects the system devices and system memory. Any one of the system devices may serve as a bus master of the system bus at any one time when communicating over the bus with each other or with system memory. In addition, the memory controller may serve as a bus master on behalf of a slave device requesting access to the system bus. The input/output devices have control logic incorporated therein for (i) determining when an alternate input/output device requests control of the bus, (ii) outputting a preemption signal in response to the alternate request, and (iii) relinquishing control of the bus in response to the preemption signal.

Abstract: An interface between a central processing unit (CPU) and a peripheral device is provided which ensures compatibility between existing software for the peripheral device and a CPU of any speed. The interface waveshapes read or write strobe signals in a transfer cycle between the peripheral device and the CPU in order to ensure timing parameters of the peripheral device are not violated by fast CPUs. If the waveshaping causes a change in the timing between first and second consecutive read or write strobe signals, the interface provides a wait signal to the CPU for the purpose of instructing it to extend the transfer cycle of the second strobe signal. In the illustrated embodiment, an interface according to the invention is part of a video interface connecting a microprocessor unit (MPU) and a video digital-to-analog converter (video DAC). Writing or reading color data to or from the video DAC occurs by way of the interface of the invention.

Abstract: A computer adapter card (204) includes a plurality of setup registers (224-226) for receiving setup parameters during initialization of the computer system. Each of the setup registers of an adapter card is accessed at the same address as the corresponding setup register of all other adapter cards in the system. The adapter card is designed to be connected to a computer bus (201) that does not include individual setup lines for each of the adapter cards in the system. To select an individual adapter card, each adapter card includes a register (214) for storing a programmable adapter card number, a plurality of switches (218) for selecting a switch selectable adapter card number, and a comparator (216) for comparing the programmable adapter card number to the switch selectable adapter card number. When an adapter card is initially installed in the computer system, the user sets the switches to correspond to the number of the adapter card slot into which the card is inserted.

Abstract: Method and apparatus for displaying a horizontal screen separator line between two screen areas. A first step operates a display screen controller (12) in a split screen mode of operation so as to display a first screen area (3) at an upper portion of a display screen (18) and a second screen area (4) at a lower portion of the display screen. The step of operating further includes a step of reading data from a screen memory (42) and displaying rows of corresponding alphanumeric characters. Each character is displayed as a plurality of image pixels arranged along a first number of horizontal scan lines. A further step displays a horizontal visual separator (2) between a last row of the first screen area and a first row of the second screen area.

Abstract: An arrangement is described for extracting charged particles which have been emitted from a sample due to the impact of a primary ion beam. The arrangement comprises an electrode arrangement effective to produce an electric potential which is non-linear along a chosen direction of travel of the particles. A system of einzel lenses is effective to match the trajectories of the particles passing from the electrode means to the analyser of a mass spectrometer.

Abstract: A video subsystem has a CRT (cathode ray tube) display, video controller and video memory for CRT data which requires access by the controller and a CPU (control processing unit). The subsystem monitors activity of the CRT screen display and the video controller and anytime CRT screen display is not required regardless of the time of occurrence, the CPU is allowed to have access to the video memory during the cycle or cycles in which such inactivity of display occurs. A guaranteed minimum number of cycles is assured for access of the video memory by the CPU using a fixed access sequence during the display periods of a high speed mode and shifting to an arbitration strategy to allow CPU access to occur during non-display times of the high speed mode so that the CPU can acquire more cycles to reduce any backlog of requests as necessary.