Abstract: Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more device-side data lanes and transceiver logic to receive a bandwidth configuration command. The transceiver logic may also configure a transmit bandwidth of the one or more device-side data lanes based on the bandwidth configuration command. Additionally, the transceiver logic can configure a receive bandwidth of the one or more device-side data lanes based on the bandwidth configuration command.

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) interface having one or more clock circuits, a power supply coupled to the one or more clock circuits, and logic to receive a rate adjustment command at the IO interface. The logic may also be configured to adjust a data rate of the IO interface in response to the rate adjustment command, and to adjust an output voltage of the power supply in response to the rate adjustment command.

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

Abstract: Disclosed is a scalable input/output interface that has multiple bays and includes a housing surrounding a plurality of pairs of substrates. A first substrate of the pair of substrates may have a first contact surface and a second substrate of the pair of substrates may have a second contact surface that opposes the first contact surface, wherein each substrate has a connection edge. At least one integrated buffer can be coupled to either the first side or the second side of each substrate. A plurality of rows of contacts can be coupled to the opposing surfaces of each substrate of the pair of substrates, wherein each row of contacts can be stacked substantially parallel to the connection edge. Each connection edge can also be coupled to a separate integrated buffer.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: According to some embodiments, a method and apparatus are provided to generate a sine wave via a jitter modulator to modulate a control voltage of a clock source. The jitter modulator is in-situ on a die. The sine wave is received at a clock and data recovery circuit comprising the clock source. The clock and data recovery circuit is in-situ on the die.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: According to some embodiments, a method and apparatus are provided to generate a sine wave via a jitter modulator to modulate a control voltage of a clock source. The jitter modulator is in-situ on a die. The sine wave is received at a clock and data recovery circuit comprising the clock source. The clock and data recovery circuit is in-situ on the die.

Abstract: Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.

Abstract: A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.

Abstract: In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.

Abstract: A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: An integrated circuit compensates for power supply voltage dependent delay using a clock circuit that is responsive to a power supply voltage measuring circuit. The clock circuit modifies a phase relationship based on a measured power supply voltage value.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to predetermined data values. The predetermined data values may be sourced from a linear feedback shift register.