Abstract: A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a data transceiver circuit. The combination data and synchronization transceiver circuit synchronizes the port with another simultaneous data port coupled to the same bus. The combination data and synchronization transceiver circuit includes a driver with a variable output impedance. Prior to synchronization, the driver has an imbalanced output impedance, and after synchronization, the driver has a substantially balanced output impedance.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: A simultaneous bidirectional data port circuit includes a current mode output driver for driving an output node and a current mode return driver for driving a differential receiver. The current mode return driver is scalable to reduce current requirements. Each driver is divided into driver segments. Some driver segments are driven by outbound data, and other driver segments are driven by pre-equalization data. Variable pre-equalization is provided by a pre-driver that selects the number of driver segments to be driven with pre-equalization data and the number of driver segments to be driven by outbound data.

Abstract: A multiple input, fully differential amplifier. Embodiments make use of complementary differential transistors pairs connected with cascode transistors to form folded cascode pairs, to achieve wide common mode range, high common mode rejection, and high gain.

Abstract: A trimmable bandgap voltage reference circuit includes variable current sources to drive variable currents through parallel combination circuits. The parallel combination circuits include variable resistors and diodes of differing sizes. Voltages developed across the parallel combination circuits are input to a differential amplifier that is used as a feedback amplifier to bias the variable current sources. The variable current sources and variable resistors can all be digitally controlled. A processor can query the operating point of the bandgap voltage reference circuit, and can also set the current and resistance values through a control circuit.

Abstract: A data receiver circuit having a comparator that exhibits substantially variable offset that is controllable to represent a variable reference level, without a separate input to receive a reference voltage level. The comparator output provides an indication of the comparison between a fixed voltage level applied to its differential signal input and the variable reference level. While changing an offset code that is fed to an offset control input of the comparator, and while applying a fixed voltage level that represents a symbol in the transmission line analog signal, a value of the offset code which causes the output of the comparator to change states is captured. A similar process may be repeated for different symbol values that can be transmitted, such that an indication of the voltage margin may be obtained as a difference between two captured offset codes. Circuitry to perform the process may be provided on-chip to the receiver circuit.

Abstract: A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

Abstract: A clock recovery circuit includes a delay locked loop, and a clock phase interpolator circuit. The delay locked loop provides multiple phases of an input clock signal to the interpolator circuit, which interpolates between two of the clock phases to provide a clock signal at a desired phase. The clock phase interpolator circuit includes selectable differential transistor pairs coupled to variable current sources. Different differential transistor pairs are driven by clock signals of different phases provided by the delay locked loop circuit. Two differential transistor pairs are selected, and currents provided to the selected differential transistor pairs are adjusted to provide an output clock of the desired phase.

Abstract: A trimmable bandgap voltage reference circuit includes variable current sources to drive variable currents through parallel combination circuits. The parallel combination circuits include variable resistors and diodes of differing sizes. Voltages developed across the parallel combination circuits are input to a differential amplifier that is used as a feedback amplifier to bias the variable current sources. The variable current sources and variable resistors can all be digitally controlled. A processor can query the operating point of the bandgap voltage reference circuit, and can also set the current and resistance values through a control circuit.

Abstract: A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

Abstract: A receiver integrated circuit (IC) die or functional unit has deskew circuitry to reduce bit-to-bit timing variation that is no more than one bit time interval in a number of bits that are received, before validating the capture of the bits using a transition in a received strobe signal. The data bits and the strobe signal are driven in a parallel bus section that may be part of a shared multi-drop bus or a point-to-point bus. The system applications include interfacing to a processor or memory bus of a computer system.

Abstract: A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

Abstract: A simultaneous bidirectional data port circuit includes a current mode output driver for driving an output node and a current mode return driver for driving a differential receiver. The current mode return driver is scalable to reduce current requirements. Each driver is divided into driver segments. Some driver segments are driven by outbound data, and other driver segments are driven by pre-equalization data. Variable pre-equalization is provided by a pre-driver that selects the number of driver segments to be driven with pre-equalization data and the number of driver segments to be driven by outbound data.

Abstract: In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.

Abstract: A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.

Abstract: According to an embodiment of the invention a circuit that is to be coupled to a reference voltage line. The circuit includes a noise coupling circuit that is to couple noise from the circuit to a reference voltage line based upon whether a driver is driving a data line.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.