Abstract: A current reference with reduced sensitivity to process variations includes a variable resistor and a control transistor. The control transistor has a generated current from source-to-drain that first passes through the variable resistor. The control transistor has a reference voltage applied to the gate, and the source-to-gate voltage is a function of the reference voltage and the voltage drop across the variable resistor. A control loop circuit measures the generated current and modifies the resistance value of the variable resistor in response. An external precision resistor is used to measure the generated current, and current variations as a result of process variations are reduced.

Abstract: A current reference with reduced sensitivity to process variations includes two current sources. The first current source has an output current that is sensitive to process variations. The second current source has, as a component of its input current, the output current of the first current source. The input current to the second current source is substantially constant because the process dependent component has been removed by the output current of the first current source. Variable resistors internal to the current source are set using a control loop circuit and an external resistor.

Abstract: In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.

Abstract: The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.

Abstract: In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

Abstract: A number of data symbols are driven into a transmission line while simultaneously driving the data symbols into another node. A difference between a signal level from the transmission line and a signal level from the other node while driving the symbols is determined. The difference is applied to a signal input of a variable offset comparator. One of a number of binary values (offset codes) are applied to an offset control input of the comparator, to adjust an implied, variable reference level of the comparator, prior to the comparator performing a comparison between the input signal and the implied reference level.

Abstract: A biased control loop for setting the impedance of an output driver includes a dummy driver having a variable output impedance, a sample and compare circuit to compare the output impedance of dummy output driver to a reference, and an up/down counter to modify the impedance. When the loop is locked, an error signal alternates positive and negative about a reference value. A digital filter produces a filtered version of the error signal with an apparent error value that does not alternate. The digital filter has a biased lock circuit that guarantees that the apparent error does not alternate. A simultaneous bidirectional port includes an output driver and the biased control loop to set the output driver impedance. When the output driver drives a bidirectional line and serves as a termination impedance for another driver, the reduced apparent error variation provides improved impedance matching.

Abstract: The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency, and without adding signal discontinuities. In an aspect, a buffer having a trigger is coupled with a component that connects to a memory bus, the buffer echoes signals to an observability port, and a diagnostic device reads the echoed signals. In an aspect, the bus is one of a simultaneous bi-directional (SBD) bus having ternary logic levels, a single ended bus, a differential bus, an optically coupled bus, a chipset bus, a frontside bus, an input/output (I/O) bus, a peripheral component interface (PCI) bus, and an industry standard architecture (ISA) bus. In an aspect, the buffer echoes bus signals having frequencies between 500 MHz. and 5 GHz. In an aspect, the buffer echoes bus signals having frequencies of at least 5 GHz.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.

Abstract: A simultaneous bi-directional I/O circuit includes a first MUX in the reference select circuitry and a second, matching MUX in the pre-driver stage of the output buffer. In normal mode, the first MUX passes the driven data output signal, which controls the threshold of the differential receiver circuit between two different non-zero voltage levels, so that the receiver circuit can properly decode an incoming signal at the I/O node or pin. In an AC switching state or loopback test mode, the first MUX deselects the driven data output signal from controlling the receiver circuit. This allows the receiver circuit to decode outgoing data that is being looped back as incoming data. The second MUX enables the reference select circuitry to switch at a rate that matches the output slew rate in order to provide high-speed operation. Also described are an electronic system, a data processing system, and various methods of testing simultaneous bi-directional I/O circuits.

Abstract: In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

Abstract: A differential amplifier has input and output terminals to generate a second signal at the output terminals for a first signal. The amplifier has feedback switches between the output terminals and the input terminals. Offset capacitors are coupled to the differential amplifier at the input terminals and reference voltages via charging switches to provide offsets for the first signal form the reference voltages via input switches.

Abstract: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

Abstract: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

Abstract: A differential amplifier is provided, incorporating negative hysteresis by automatic reference voltage adjustment. A delayed output signal is routed to a switch or multiplexer which functions to select one of two reference voltage levels, creating negative hysteresis. The delayed output signal is delayed by a series of inverters, which prevent certain embodiments of the invention from oscillating under some conditions. The two reference voltage levels are selected to be near the respective data signal input high and low signal voltage levels, but far enough from these levels so as not to be adversely affected by noise or other interference.

Abstract: A voltage-controlled CMOS delay cell includes a pair of inverters and a pair of load cells. The load cells are controllable by independent N and P bias control voltages to vary the delay of the delay cell. Symmetric P and N load capacitors in the delay cells, together with the N and P bias control voltages, provide effective rejection of noise on the power supply rails and enable the delay cell to generate symmetric low-going and high-going delays. The P bias control voltage is generated from the N bias control voltage by a closed-loop voltage control circuit. Also described are a voltage-controlled load cell, an integrated circuit, an electronic system, and a data processing system that incorporate one or more of the symmetric CMOS voltage-controlled delay cells.

Abstract: A frequency control unit has an input to receive a digital downstream strobe signal and an output to provide a controlled delay to the input strobe signal. A downstream latch has a data input to receive a digital downstream data signal and a clock input coupled to the output of the frequency control unit. The controlled delay is essentially equal to a set up time of the latch. A delay element coupled to the output of the frequency control unit further delays the downstream strobe signal by essentially a propagation time of the latch. Output drivers are coupled to the outputs of the latch and the delay element.

Abstract: A latch having a pass gate, multiple clock paths connected to the pass gate, and a data path connected to the pass gate, wherein the data path and the multiple clock paths have the same number and types of elements.

Abstract: A differential delay cell includes load transistors and a current source transistor biased linearly. The delay control input of the differential delay cell is also the power supply input such that when the power supply voltage changes, the delay in the differential delay cell changes. The resistance presented by the load transistors changes as a function of the power supply voltage, as does the current sourced by the variable current source. The combination of changing resistance and changing current as the power supply voltage changes results in a substantially constant output voltage swing. A ring of differential delay cells is included in a voltage controlled oscillator, which is in turn included in a phase lock loop. The phase lock loop has a wide loop bandwidth and the voltage controlled oscillator has a good power supply rejection ratio.