Abstract: Embodiments for a terrain following (TF) radar configured for use in an airborne system are generally described herein. In some embodiments, a radar return comprising dual polarimetry radar data is processed to determine a Correlation Coefficient (CC), a Differential Reflectivity (ZDR), and a Specific Differential Phase (KDP). Discriminator logic is applied to the CC, the ZDR and the KDP to determine whether the radar return comprises solely rain. Further signal processing may be performed on the radar return when the radar return does not comprise solely rain. When the radar signal comprises solely rain, the radar return is tagged as a rain return. Applying the discriminator logic may include applying linear and/or quadratic functions to the CC, the ZDR and the KDP to determine whether the radar return comprises solely rain.

Abstract: Embodiments for a terrain following (TF) radar configured for use in an airborne system are generally described herein. In some embodiments, a radar return comprising dual polarimetry radar data is processed to determine a Correlation Coefficient (CC), a Differential Reflectivity (ZDR), and a Specific Differential Phase (KDP). Discriminator logic is applied to the CC, the ZDR and the KDP to determine whether the radar return comprises solely rain. Further signal processing may be performed on the radar return when the radar return does not comprise solely rain. When the radar signal comprises solely rain, the radar return is tagged as a rain return. Applying the discriminator logic may include applying linear and/or quadratic functions to the CC, the ZDR and the KDP to determine whether the radar return comprises solely rain.

Abstract: A technique includes an access controller of a programmable logic device providing password protection-based access to a memory of the programmable logic device. The programmable logic device initiates programming of the access controller with a password; and in response to the programmable logic device detecting a predetermined stimulus, the programmable logic device initiates communication of the password to the access controller to unlock access to the memory.

Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

Abstract: Method and apparatus are provided for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

Abstract: The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell associated with a first digit line to a first data value, programming a second memory cell associated with a second digit line to a second data value, the second data value being complementary with respect to the first data value, firing a first sense amplifier associated with the first digit line, firing a second sense amplifier associated with the second digit line after a time delay with respect to the act of firing the first sense amplifier associated with the first digit line, detecting a measured data value associated with the second digit line, and comparing the measured data value to the second data value to determine whether the first digit line is short circuited to the second digit line.

Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

Abstract: A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

Abstract: Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

Abstract: Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

Abstract: A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

Abstract: Method and apparatus are disclosed for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.

Abstract: A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

Abstract: The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell associated with a first digit line to a first data value, programming a second memory cell associated with a second digit line to a second data value, the second data value being complementary with respect to the first data value, firing a first sense amplifier associated with the first digit line, firing a second sense amplifier associated with the second digit line after a time delay with respect to the act of firing the first sense amplifier associated with the first digit line, detecting a measured data value associated with the second digit line, and comparing the measured data value to the second data value to determine whether the first digit line is short circuited to the second digit line.

Abstract: Method and apparatus for regulating an antifuse programming current by lightly doping an electrically connected region so that the resistance of the region responds in a non-linear manner to changes in voltage. In this way a variable resistor or a variably resistive transistor may be created which vary their resistance in response to an applied voltage and which may thereby limit a programming current while not limiting a lesser, reading current to a serially connected antifuse.

Abstract: A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

Abstract: A balanced sense amplifier control for open digit line architecture memory devices. Firing of the sense amplifiers on each side of a section of a memory device is controlled by a two stage NAND gate logic circuit that utilizes a tree routing scheme. By gating the global signal with a section signal through the two stage NAND gate logic circuit, the sense amplifiers on each side of a section can be fired simultaneously.

Abstract: An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

Abstract: The antifuse device comprises an insulating layer positioned in the trench, a conductive member positioned above the insulating layer, at least a portion of the conductive member being positioned within the trench, the conductive member adapted to have at least one programming voltage applied thereto, and at least one doped active region formed in the substrate adjacent the trench. The antifuse further comprises at least one conductive contact coupled to the conductive member, and at least one conductive contact coupled to the doped active region.