Abstract: An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.

Abstract: A data storage device includes a memory die. The memory die includes a memory having a three-dimensional (3D) memory configuration. A method includes sensing information stored at a region of the memory to generate sensed information. The method further includes adjusting one or more write parameters associated with the region in response to an error rate associated with the sensed information satisfying an error threshold.

Abstract: A method includes initiating a first decode operation of data at an error correction code (ECC) hard bit decoder in a data storage device that includes a controller and a memory. The method further includes, in response to the first decode operation indicating that the data is uncorrectable by the first decode operation, identifying one or more bits of the data that correspond to a disturb condition test pattern, changing a value of the one or more identified bits of the data to generate modified data, and initiating a second decode operation at the ECC hard bit decoder using the modified data.

Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count.

Abstract: A data storage device includes a memory including a group of storage elements. The memory is configured to read the group of the storage elements. A controller is coupled to the memory. The controller is configured to, in response to a first error correction code (ECC) procedure determining that a first plurality of bit values obtained using a first read voltage to read the group of storage elements is uncorrectable, instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values. The controller is further configured to compare the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values and to change one or more values of the first plurality of bit values for one or more bits in the first set of bits to generate a first plurality of corrected bit values.

Abstract: A data storage device includes non-volatile memory and a controller. The controller is configured to read first data from the non-volatile memory. The first data indicates a first count of storage elements of the group that have a first activation status when sensed with a first reference voltage at a first time. The controller is configured to read second data from the non-volatile memory. The second data indicates a second count of storage elements of the group that have the first activation status when sensed with the first reference voltage at a second time. The controller is configured to generate an updated first reference voltage at least partially based on a difference between the first count and the second count and based on one or more parameters corresponding to a distribution of threshold voltages of storage elements at the first time.

Abstract: An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupled to a first serializer/deserializer communication interface of a memory controller.

Abstract: A method of managing wear leveling in a data storage device includes determining whether a reliability measurement associated with a first portion of a first nonvolatile memory die satisfies a threshold. The first nonvolatile memory die is included in a plurality of memory dies. The method includes, in response to determining that the reliability measurement associated with the first portion of the first nonvolatile memory die satisfies the threshold, transferring first data from the first portion of the first nonvolatile memory die to a second nonvolatile memory die of the plurality of memory dies.

Abstract: An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.

Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.

Abstract: An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the multiple memory cells.

Abstract: An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The apparatus includes a second semiconductor device coupled to the first semiconductor device. The second semiconductor device includes a charge pump, and the 3D memory does not include a charge pump.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular W/E counter and that includes a storage element that is tracked by a particular cell erase counter of the set of counters. The method includes, in response to the value of the particular W/E counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory at least partially based on the value of the particular cell erase counter.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter. Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters. The method includes, in response to the value of the particular counter indicating that a count of read accesses to the particular region equals or exceeds a first threshold, initiating a remedial action to the particular region of the non-volatile memory.

Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes comparing, in the controller, a count of erase pulses to an erase pulse threshold. The count of erase pulses corresponds to a particular region of the non-volatile memory. The method includes, in response to the count of erase pulse satisfying the erase pulse threshold, initiating a remedial action with respect to the particular region of the non-volatile memory.

Abstract: A data storage device includes a memory including a group of storage elements. The memory is configured to read the group of the storage elements. A controller is coupled to the memory. The controller is configured to, in response to a first error correction code (ECC) procedure determining that a first plurality of bit values obtained using a first read voltage to read the group of storage elements is uncorrectable, instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values. The controller is further configured to compare the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values and to change one or more values of the first plurality of bit values for one or more bits in the first set of bits to generate a first plurality of corrected bit values.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. The method includes, in response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory.

Abstract: A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.

Abstract: In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (CEC) is at least as large as a target error correction code page count (TEC). The CEC is a page count of error correction code (ECC) pages of data read from the memory during a time period from a previous time to a particular time using a set of reference voltages. In response to the CEC being at least as large as the TEC, the method includes updating a subset of the set of reference voltages conditioned upon a difference between a current mean error count (CMEC) and a previous mean error count being at least as large as a target mean delta error. The CMEC is based on a count of read errors associated with the ECC pages read during the time period.