Abstract: A sense amplifier uses a cascode stage (76 or 100) that receives a predetermined bit line pair differential signal and provides an output. The cascode stage output is coupled to a true and a complement output of the sense amplifier. In one form, a pair of pass transistors (77, 78) and an amplifier (79) are coupled to the cascode stage and to complementary outputs and are controlled by a sense enable signal. The amplifier is operative only when the pair of pass transistors are made nonconductive. In another form, the cascode stage is connected directly to a bit line pair differential signal and to sense nodes (82, 86) that are separately coupled to a data line pair by a coupler (102) and an amplifier (104).

Abstract: Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.

Abstract: A buffer circuit (60) that includes a current source (74) having an output, the current source to provide a substantially constant current, a first differential amplifier (62), and a second differential amplifier (66). The current from current source 74 is shared by the first (62) and second (64) differential amplifiers.

Abstract: A layout portion (20) has a first portion (25), and a second portion (55). In the first portion (25), a reference voltage line (27) is disposed between two V.sub.DD power supply lines (26, 30) for a first predetermined length, for providing capacitive coupling between V.sub.DD and a reference voltage. In the second portion (55), the reference voltage line (27) is disposed between two V.sub.SS power supply lines (28, 41) for a second predetermined length, for providing capacitive coupling between V.sub.SS and the reference voltage. The capacitive coupling stabilizes the reference voltage with respect to the power supply voltage, and reduces power supply noise due to lead inductance and changing current demand. In addition, the power supply lines (26, 28, 30, 41) are disposed half above an N-type region (22) and half above a P-type substrate (21) for reducing local transistor switching noise.

Abstract: A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

Abstract: An ECL multiplexing circuit (20) includes two differential pairs (21 and 22) for receiving first and second ECL level input signals, emitter-follower output transistors (27 and 28), and a differential pair (31 and 32) for receiving differential clock signals. The differential clock signals control which of the two differential pairs (21 and 22) is coupled to the emitter-follower output transistors (27 and 28). The ECL level input signals that control a logic state of the output signals is determined by the logic state of the clock signals. The ECL multiplexing circuit (20) receives non-overlapping clock signals and is used in a quadrature frequency divide-by-two circuit (40) to divide a frequency of an input clock signal by two.

Abstract: A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock signal to a delayed clock signal from the VCD circuit (260). In response, the arbiter circuit (264) provides a retard signal to the VCD control circuit (265). The VCD control circuit (265) receives the retard signal and adjusts a propagation delay of the delayed clock signal to compensate for changes in the clock frequency, as well as to compensate for process, temperature, and power supply variations.

Abstract: A delay locked loop (44) includes an arbiter circuit (86), a VCD circuit (85), and a collapse detector (88). The arbiter circuit (86) receives an input signal and provides a retard signal to adjust the amount of propagation delay of VCD circuit (85), in order to synchronize the phases of the input signal to an output signal of the VCD circuit (85). The collapse detector (88) detects if the output signal of the VCD circuit (85) has failed to change logic states within a predetermined length of time. The delay locked loop (44) can lock the phases of two signals having different frequencies.

Abstract: A latching ECL to CMOS input buffer (20) has an input buffer (21) for receiving an ECL input signal, a CMOS latch (35), and driver circuits (55, 65). Transmission gates (31, 32) are used to couple the input buffer (21) to the latch (35) in response to a CMOS clock signal being a logic low. The driver circuits (55, 65) are coupled to transmission gates (31, 32). While the clock signal is a logic low, input nodes of the first and second driver circuits (55, 65) are precharged to a relatively high voltage in order to isolate the input signal from the first and second driver circuits (55, 65). The latch (35) both latches the logic state of the ECL input signal and converts the ECL input signal to CMOS logic levels. This allows an input signal to be latched and level converted within a relatively short period of time.

Abstract: A bit line load (380) is coupled to a bit line pair and includes bipolar pull up transistors (389, 403), P-channel load transistors (390, 404), a NAND logic gate (395), and a P-channel equalization transistor. The NAND logic gate (395) senses a differential voltage on the bit line pair, and provides an equalization signal. When a write control signal indicates the end of a write cycle, the equalization signal initiates precharge and equalization of the bit line pair.

Abstract: A synchronous memory (20) has parallel data output registers (34) and a dummy path (46). The output data from a memory array (22) is provided to the parallel output registers (34). The output registers (34) provide two parallel, interleaved, output data paths. The data in each path changes every other cycle of a clock signal. Dummy path (46) contains delay elements that model a propagation delay for a data path of the memory (20) during a read cycle. Using parallel data output registers (34) increases a time in which data is valid during the read cycle. The dummy path (46) tracks the output data signal in terms of process, power supply and temperature variations to ensure that the correct data is acquired during the read cycle.

Abstract: A pipelined memory (20) has a synchronous operating mode and an asynchronous operating mode. The memory (20) includes output registers (34) and output enable registers (48) which are used to electrically switch between the asynchronous operating mode and the synchronous operating mode. In addition, in the synchronous operating mode, the depth of pipelining can be changed between a three stage pipeline and a two stage pipeline. By changing the depth of pipelining, the memory (20) can operate using a greater range of clock frequencies. In addition, the operating frequency can be changed to facilitate testing and debugging of the memory (20).

Abstract: A memory (50) having a BICMOS sense amplifier (20) includes a differential amplifier stage (11), emitter-follower input transistors (25 and 26), and emitter-follower output transistors (27 and 28). When sense amplifier (20) is deselected, P-channel transistors (31-37) pull the bases of the bipolar transistors (23-28) to V.sub.DD -2V.sub.BE and P-channel transistors (29 and 30) decouple the bases of emitter-follower output transistors (27 and 28) from the collectors of transistors (23 and 24). At the same time, N-channel transistors (38, 40, 42, 44, and 46) decouple N-channel transistors (39, 41, 43, 45, and 47) from the emitters of bipolar transistors (23-28). Thus, no current can flow, reducing the power consumption of sense amplifier (20). Also, bipolar transistors (23-28) are prevented from being excessively reverse-biased. Additionally, a plurality of sense amplifiers (20) can have their outputs wired-OR connected.

Abstract: A memory (20) has a plurality of columns of memory cells and has a plurality of redundant columns of memory cells. A comparator (45) detects an access to a defective column. A redundant write generator (31) and write fuses (32) are provided for each write portion (30A, 30B, 30C, and 30D) to replace the defective column with a redundant column by replacing a write global data line (37) with a redundant write global data line (39). Redundant read generators (60 and 61) and read fuses (59) are provided for each read portion (50A, 50B, 50C, and 50D) to replace a defective column by deselecting a read global data line (29) and replacing it with a redundant read global data line (44). The fuses and redundant generators are located close to their global data lines, thus reducing the routing of control signals and improving the access time of redundant columns.

Abstract: An ECL logic gate (70) includes a voltage protection clamp (60) for protecting a first bipolar transistor (58) from being too heavily reverse biased when an input signal A.sub.IN is pulled to V.sub.SS. The ECL logic gate (70) includes an emitter-follower input stage and a differential amplifier stage. A voltage protection clamp (60) includes a second transistor (52) and a resistor (53) and acts to divide the amount of reverse bias on the first bipolar transistor (58) between a third transistor (51) and the first transistor (58), thereby bringing the reverse bias voltage on the first transistor (58) within acceptable levels to prevent degradation of the first transistor (58).

Abstract: A BICMOS combined bit line load and write gate for a memory comprises first and second portions coupled to first and second bit lines of a bit line pair, the first and second portions each comprising first through sixth transistors. The first and second transistors are serially coupled from a power supply voltage terminal to form a CMOS inverter whose input terminal receives a local write signal and whose output terminal is coupled to the base of the fifth transistor. The third transistor has a drain coupled to the source of the second transistor, a gate for receiving the local write signal, and a source for receiving a data signal. The fourth transistor is serially coupled between the base of the fifth transistor and the source of the third transistor, with the local write signal coupled to the gate thereof. The fifth transistor has a collector coupled to the power supply voltage terminal, and an emitter coupled to a corresponding bit line.

Abstract: A circuit enabling the conversion of a set of ECL and a set of CMOS logic levels has a differential amplifier, two emitter followers, a current switching circuit, and a level shifting circuit. The differential amplifier provides a common mode input to two emitter followers which switch very rapidly using ECL voltage levels. High operational speed is accomplished by providing a relaxation current during logic high-to-low voltage transients. The current switching circuit conserves power consumption by switching off the relaxation current during logic low-to-high transients, during which time the emitter followers switch sufficiently fast. The level shifting circuit converts the set of ECL logic voltage levels to a set of CMOS voltage levels and the CMOS output voltage is used to control the current switching circuit without introducing a switching delay time.

Abstract: A high speed logic circuit with reduced quiescent current receives a plurality of input signals and performs a predetermined logic operation on the plurality of input signals. The predetermined logic operation may be, for example, a comparison of true and complement input signals, or a logical AND of two input signals. In response to the predetermined logic operation, first and second bipolar transistors coupled between first and second power supply voltage terminals are alternately made conductive to provide an output signal therebetween at ECL levels. A biasing portion ensures a proper voltage on a base of the second bipolar transistor. A current portion draws current from the base of the second bipolar transistor until the voltage of the output signal reaches a logic low voltage, and then makes the second transistor nonconductive, keeping the quiescent current of the circuit to a minimum.

Abstract: A memory which senses output signals from a selected memory cell during a read cycle using a non-address transition detection apparatus. The memory has a plurality of memory cells which provide signals to a pair of bit lines when selected. An input circuit drives word lines and select a bit line pair of a memory cell located at the intersection of a selected word line and a selected bit line pair. The memory cell outputs bit line signals which are sensed by a combination of a differential amplifier, a level shifter, and a transconductance amplifier, and are thereafter output and presented externally at a logic state representative of a differential current at outputs of the transconductance amplifier. The combination sensing apparatus and a method for constructing such an apparatus decrease access time significantly over a prior art memory using address transition detection.

Abstract: A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.