Patents by Inventor Stephen Wise
Stephen Wise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11048174Abstract: A method, and associated apparatus and computer program, to determine corrections for a parameter of interest, such as critical dimension, of a patterning process. The method includes determining an exposure control correction for an exposure control parameter and, optionally, determining a process control correction for a process control parameter, based upon a measurement of the parameter of interest of a structure, and an exposure control relationship and a process control relationship. The exposure control relationship describes the dependence of the parameter of interest on the exposure control parameter and the process control relationship describes the dependence of the parameter of interest on the process control parameter. The exposure control correction and process control correction may be co-optimized to minimize variation of the parameter of interest of subsequent exposed and processed structures relative to a target parameter of interest.Type: GrantFiled: February 16, 2017Date of Patent: June 29, 2021Assignees: ASML Netherlands B.V., LAM Research CorporationInventors: Michael Kubis, Marinus Jochemsen, Richard Stephen Wise, Nader Shamma, Girish Anant Dixit, Liesbeth Reijnen, Ekaterina Mikhailovna Viatkina, Melisa Luca, Johannes Catharinus Hubertus Mulkens
-
Publication number: 20200233311Abstract: A method, and associated apparatus and computer program, to determine corrections for a parameter of interest, such as critical dimension, of a patterning process. The method includes determining an exposure control correction for an exposure control parameter and, optionally, determining a process control correction for a process control parameter, based upon a measurement of the parameter of interest of a structure, and an exposure control relationship and a process control relationship. The exposure control relationship describes the dependence of the parameter of interest on the exposure control parameter and the process control relationship describes the dependence of the parameter of interest on the process control parameter. The exposure control correction and process control correction may be co-optimized to minimize variation of the parameter of interest of subsequent exposed and processed structures relative to a target parameter of interest.Type: ApplicationFiled: February 16, 2017Publication date: July 23, 2020Inventors: Michael KUBIS, Marinus JOCHEMSEN, Richard Stephen WISE, Nader SHAMMA, Girish Anant DIXIT, Liesbeth REIJNEN, Ekaterina Mikhailovna VIATKINA, Melisa LUCA, Johannes Catharinus Hubertus MULKENS
-
Patent number: 10546743Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: GrantFiled: January 18, 2018Date of Patent: January 28, 2020Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Carl Radens, Richard Stephen Wise, Yiheng Xu, Yannick Loquet, Hsueh-Chung Chen
-
Publication number: 20180144926Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: ApplicationFiled: January 18, 2018Publication date: May 24, 2018Inventors: John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Carl Radens, Richard Stephen Wise, Yiheng Xu, Yannick Loquet, Hsueh-Chung Chen
-
Patent number: 9786551Abstract: An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.Type: GrantFiled: April 29, 2014Date of Patent: October 10, 2017Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Hongguang Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise
-
Patent number: 9659820Abstract: A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: GrantFiled: May 2, 2016Date of Patent: May 23, 2017Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC.Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen Spooner, Nicole A. Saulnier
-
Patent number: 9658523Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: GrantFiled: March 31, 2014Date of Patent: May 23, 2017Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Terry Spooner, Nicole A. Saulnier
-
Publication number: 20160247722Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen Spooner, Nicole A. Saulnier
-
Patent number: 9391020Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: GrantFiled: June 25, 2014Date of Patent: July 12, 2016Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen Spooner, Nicole A. Saulnier
-
Patent number: 9214429Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: GrantFiled: December 5, 2013Date of Patent: December 15, 2015Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Hsueh-Chung Chen, Lawrence A. Clevenger, Yann Mignot, Carl Radens, Richard Stephen Wise, Yannick Loquet, Yiheng Xu
-
Publication number: 20150311113Abstract: An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.Type: ApplicationFiled: April 29, 2014Publication date: October 29, 2015Applicants: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Hongguang Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise
-
Publication number: 20150279780Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: ApplicationFiled: June 25, 2014Publication date: October 1, 2015Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen SPOONER, Nicole A. SAULNIER
-
Publication number: 20150279784Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Applicants: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Terry Spooner, Nicole A. Saulnier
-
Publication number: 20150162277Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicants: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Carl Radens, Richard Stephen Wise, Yiheng Xu, Yannick Loquet, Hsueh-Chung Chen
-
Publication number: 20150162278Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicants: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: John H. Zhang, Hsueh-Chung Chen, Lawrence A. Clevenger, Yann Mignot, Carl Radens, Richard Stephen Wise, Yannick Loquet, Yiheng Xu
-
Patent number: 8829612Abstract: A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.Type: GrantFiled: January 3, 2011Date of Patent: September 9, 2014Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Xi Li, Richard Stephen Wise
-
Patent number: 8777608Abstract: A gas burner ignition system, includes a power circuit (1), igniter (3), a solenoid valve (6); an igniter switch control circuit (2) which is connected between the power circuit (1) and igniter (3); a solenoid valve switch control circuit (5) connected between the power circuit (1) and the solenoid valve (6); the solenoid valve switch control circuit (5) and the igniter switch control circuit (2) are responsive to delay circuit (4), so that the user need only operate the control knob without the need to hold the operating knob until the thermocouple (42) has reached operating temperature.Type: GrantFiled: July 17, 2008Date of Patent: July 15, 2014Assignee: Aktiebolaget ElectroluxInventors: Raymond Cheok Liang Wah, Weijie Pan, Yu Xuejing, Stephen Wise
-
Patent number: 8701651Abstract: A modular trivet arrangement includes trivet members including a first bar, a first footing at a first end of the first bar, a second footing at the second end of the first bar, and one or more transverse bars, each transverse bar being transverse to the first bar and intersecting therewith, the second bar having a third footing at a first end of the second bar and a fourth footing at the second end of the second bar. The intersection between the first and second bars can support a cooking utensil. The modular trivet members include one or more engaging slots adapted to enable engagement with a cooperating modular trivet member.Type: GrantFiled: April 2, 2009Date of Patent: April 22, 2014Assignee: Aktiebolaget ElectroluxInventors: Scott King, Lyndon Craig, Lars Erikson, Carlo Rossi, Stephen Wise
-
Patent number: 8492295Abstract: A semiconductor structure fabrication method. A provided structure includes: a semiconductor substrate, a transistor on the semiconductor substrate, N interconnect layers on the semiconductor substrate, and a temporary filling region within the N layers. N is at least 2. The temporary filling region is heated at a high temperature sufficiently high to result in the temporary filling material being replaced by a cooling pipes system that does not include any solid or liquid material. A first portion and a second portion of the cooling pipes system are each in direct physical contact with a surrounding ambient at a first interface and a second interface respectively such that a first direction perpendicular to the first interface is perpendicular to a second direction perpendicular to the second interface. A totality of interfaces between the cooling pipes system and the ambient consists of the first interface and the second interface.Type: GrantFiled: September 13, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Kaushik A. Kumar, Andres Fernando Munoz, Michael Ray Sievers, Richard Stephen Wise
-
Patent number: D770503Type: GrantFiled: March 2, 2015Date of Patent: November 1, 2016Assignee: PASSWORDBOSS, LLCInventor: Stephen Wise