Patents by Inventor Steve Cho
Steve Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096809Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein.Type: ApplicationFiled: September 15, 2022Publication date: March 21, 2024Applicant: Intel CorporationInventors: Hiroki Tanaka, Robert Alan May, Onur Ozkan, Ali Lehaf, Steve Cho, Gang Duan, Jieping Zhang, Rahul N. Manepalli, Ravindranath Vithal Mahajan, Hamid Azimi
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Patent number: 11935857Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).Type: GrantFiled: September 23, 2022Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Kristof Darmawaikarta, Robert May, Sashi Kandanur, Sri Ranga Sai Boyapati, Srinivas Pietambaram, Steve Cho, Jung Kyu Han, Thomas Heaton, Ali Lehaf, Ravindranadh Eluri, Hiroki Tanaka, Aleksandar Aleksov, Dilan Seneviratne
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Publication number: 20240006298Abstract: An electronic device may include an integrated circuit, for instance a semiconductor die. The electronic device may include a substrate having a first layer and a second layer. The first and second layers may include interconnects recessed below a surface of the substrate. The substrate may include a passivation layer directly coupled with portions of the interconnects. A solder resist material may at least partially cover portions of the passivation layer directly coupled with the first interconnect surface.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Suddhasattwa Nad, Steve Cho, Marcel Arlan Wall, Onur Ozkan, Ali Lehaf, Yi Yang, Jason Scott Steill, Gang Duan, Brandon C. Marin, Jeremy D. Ecton, Srinivas Venkata Ramanuja Pietambaram, Haifa Hariri, Bai Nie, Hiroki Tanaka, Kyle Mcelhinny, Jason Gamba, Venkata Rajesh Saranam, Kristof Darmawikarta, Haobo Chen
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Publication number: 20230343769Abstract: Embodiments of a microelectronic assembly comprise a microelectronic assembly, comprising: a stack of layers coupled by at least fusion bonds; a package substrate coupled to a first layer in the stack of layers; one or more dies in the first layer; and one or more dies in a second layer in the stack of layers, the second layer coupled to the first layer, wherein: a copper lining is between adjacent surfaces of any two adjacent dies in at least one of the first layer and the second layer, and the copper lining contacts and substantially covers the adjacent surfaces. In various embodiments, the dies comprise dummy dies and integrated circuit (IC) dies, the dummy dies are one of: semiconductor dies without any ICs, and semiconductor dies having non-functional ICs, and the IC dies comprise semiconductor dies having functional ICs.Type: ApplicationFiled: April 25, 2022Publication date: October 26, 2023Applicant: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Steve Cho, Babak Sabi
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Patent number: 11735558Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: GrantFiled: May 10, 2022Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Anurag Tripathi, Takeshi Nakazawa, Steve Cho
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Patent number: 11699648Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.Type: GrantFiled: March 9, 2022Date of Patent: July 11, 2023Assignee: Tahoe Research, Ltd.Inventors: Srinivas V. Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
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Publication number: 20230096835Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes operational bridge bumps to electrically connect the die to a bridge within the substrate. The apparatus also includes dummy bumps adjacent the operational bridge bumps.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Kyle McElhinny, Bohan Shan, Hongxia Feng, Xiaoying Guo, Adam Schmitt, Jacob Vehonsky, Steve Cho, Leonel Arana
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Publication number: 20230097624Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Kyle McElhinny, Onur Ozkan, Ali Lehaf, Xiaoying Guo, Steve Cho, Leonel Arana, Jung Kyu Han, Srinivas Pietambaram, Sashi Kandanur, Alexander Aguinaga
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Publication number: 20230095281Abstract: Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes bumps to electrically couple the die to the substrate. Ones of the bumps have corresponding bases. The bases have a shape that is non-circular.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Kyle McElhinny, Hongxia Feng, Xiaoying Guo, Steve Cho, Jung Kyu Han, Changhua Liu, Leonel Arana, Rahul Manepalli, Dingying Xu, Amram Eitan
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Publication number: 20230086180Abstract: A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Onur Ozkan, Edvin Cetegen, Steve Cho, Nicholas S. Haehn, Jacob Vehonsky, Gang Duan
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Publication number: 20230086649Abstract: An apparatus is described. The apparatus includes I/O structures having pads and solder balls to couple with a semiconductor chip, wherein, a first subset of pads and/or solder balls of the pads and solder balls that approach the semiconductor chip during coupling of the semiconductor chip to the I/O structures are thinner than a second subset of pads and/or solder balls of the pads and solder balls that move away from the semiconductor chip during the coupling of the semiconductor chip to the I/O structures.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Onur OZKAN, Edvin CETEGEN, Steve CHO, Nicholas S. HAEHN, Jacob VEHONSKY
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Publication number: 20230015619Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).Type: ApplicationFiled: September 23, 2022Publication date: January 19, 2023Inventors: Kristof DARMAWAIKARTA, Robert MAY, Sashi KANDANUR, Sri Ranga Sai BOYAPATI, Srinivas PIETAMBARAM, Steve CHO, Jung Kyu HAN, Thomas HEATON, Ali LEHAF, Ravindranadh ELURI, Hiroki TANAKA, Aleksandar ALEKSOV, Dilan SENEVIRATNE
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Patent number: 11488918Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).Type: GrantFiled: October 31, 2018Date of Patent: November 1, 2022Assignee: Intel CorporationInventors: Kristof Darmawaikarta, Robert May, Sashi Kandanur, Sri Ranga Sai Boyapati, Srinivas Pietambaram, Steve Cho, Jung Kyu Han, Thomas Heaton, Ali Lehaf, Ravindranadh Eluri, Hiroki Tanaka, Aleksandar Aleksov, Dilan Seneviratne
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Publication number: 20220270998Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Applicant: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Anurag Tripathi, Takeshi Nakazawa, Steve Cho
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Patent number: 11373972Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: GrantFiled: June 16, 2020Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Anurag Tripathi, Takeshi Nakazawa, Steve Cho
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Publication number: 20220199515Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Inventors: Srinivas V. PIETAMBARAM, Jung Kyu HAN, Ali LEHAF, Steve CHO, Thomas HEATON, Hiroki TANAKA, Kristof DARMAWIKARTA, Robert Alan MAY, Sri Ranga Sai BOYAPATI
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Patent number: 11309239Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.Type: GrantFiled: October 20, 2020Date of Patent: April 19, 2022Assignee: Intel CorporationInventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati
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Publication number: 20210391294Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Intel CorporationInventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Anurag Tripathi, Takeshi Nakazawa, Steve Cho
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Publication number: 20210035901Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Srinivas V. PIETAMBARAM, Jung Kyu HAN, Ali LEHAF, Steve CHO, Thomas HEATON, Hiroki TANAKA, Kristof DARMAWIKARTA, Robert Alan MAY, Sri Ranga Sai BOYAPATI
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Patent number: 10854541Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.Type: GrantFiled: August 28, 2019Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Srinivas Pietambaram, Jung Kyu Han, Ali Lehaf, Steve Cho, Thomas Heaton, Hiroki Tanaka, Kristof Darmawikarta, Robert Alan May, Sri Ranga Sai Boyapati