Abstract: In one embodiment, a method for recycling soap includes scraping the surface of a soap bar using a bladed implement; soaking the soap bar in a cleansing solution including dimethyl benzylammonium chlorides monohydrate; placing the soap bar on a rack in a Rational Clima Plus Combi unit; placing a pan under the rack; steaming the soap bar using the Rational Clima Plus Combi unit for five minutes at 212° F.; cooling the soap bar in a refrigerator unit at 38° F. for at least seven minutes; and packaging the soap for reuse.

Abstract: A power controller which is installed on each of a plurality of blades in a blade style server computer. Each power controller determines whether the blade it is on can go to a higher power mode without a command from a centralized controller.

Abstract: The invention is a system and method for eliminating the requirement for chips or tokens that are traditionally used in standard gaming.

Abstract: Shielding for a blade server style computer wherein each individual blade is surrounded with shielding.

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: A backpane which receives a plurality of printed circuit boards and the backpane has air holes to allow ventilation.

Abstract: A specialized processing chip (e.g. a graphics accelerator) in which the host interface provides access to the diagnostic registers in most of the complex logic on the chip, except for the host interface itself. This advantageously permits the host CPU to obtain direct access to register contents in the specialized chip.

Abstract: System and method for testing the error detection and correction (“ECC”) capabilities of an ECC memory controller are disclosed. The system uses the natural state of the bus to induce one- or two-bit memory errors by disabling the ECC capabilities of the controller and then writing a test data pattern that is one or two bits different than a data pattern that would result in an ECC code equal to the natural state of the bus and an ECC code equal to the natural state of the bus to a selected memory location. At that point, the ECC capabilities of the memory controller are reenabled and the memory location to which the test data pattern was previously written is read and its ECC code generated. A determination is then made whether the memory controller detected and/or corrected the induced error.

Abstract: A system and method for testing the snoop capabilities of a read-only code cache system. A test code sequence for testing the snooping operations of the read-only code cache is first loaded into system memory, and an identical copy of the test code sequence is loaded into the read-only code cache system at the same address. A direct memory access (DMA) transfer is then initiated to transfer one or more instructions to overwrite a portion of the system memory where the test code sequence is located. If the snooping functions of the read-only code cache are operating properly, the code cache will detect the cycles and invalidate the respective lines in the code cache where the instructions are located. Upon completion of the direct memory access transfer, the CPU performs the remainder of the test code sequence and determines whether the snooping operations performed properly.