Abstract: A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.

Abstract: A method is disclosed to effectively achieve a low deposition temperature of CMO memory materials by depositing the CMO memory material at relatively low temperatures that give an amorphous film, then to later melt and re-crystallize the CMO memory material with a laser (laser annealing).

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element. The multi-resistive state element is sandwiched between the electrodes such that the top face of the bottom electrode is in contact with the multi-resistive state element's bottom face and the bottom face of the top electrode is in contact with the multi-resistive state element's top face. The bottom electrode, the top electrode and the multi-resistive state element all have sides that are adjacent to their faces. Furthermore, the sides are at least partially covered by a sidewall layer.

Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.

Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

Abstract: Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.

Abstract: A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may include metal lines and barrier layers. Such structures are then exposed to the high temperature processing steps and should be resistant to such temperatures.

Abstract: A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or insulating materials of single-crystalline, poly-crystalline or amorphous structure while containing current carrier traps whose respective energy levels and degrees of carrier occupancy, modifiable by the height and width of an applied write voltage pulse, determine the resistance. The mechanism of modification can be through carrier tunneling, free carrier capturing, trap-hopping conduction or Frenkel-Poole conduction. The current carrier traps can be created with dopant varieties or an initialization procedure.

Abstract: An apparatus, system, and method are provided for automatically freeing locked server resources using a timeout value closely related to actual real-time message delays plus a delta value that can be adjusted at a plurality of levels. The levels include default, server, connection, and transaction. The apparatus includes a timer, a communication module, a computation module, and a lock handler. The timer determines a timeout value for communications from a client to a server. The communication module sends an output message to the client and locks a server resource in anticipation of an acknowledgement (ACK) message from the client. The computation module, which calculates an ACK timer, includes a difference between a send time and a current time. If no ACK message has been received from the client and the ACK timer exceeds the timeout value, the lock handler may free the locked server resource.

Abstract: An apparatus, system, and method are disclosed for directly accessing a database management system (“DBMS”). A client communication module is included to transmit a data call between a client and a client interface wherein the client interface resides within a database network. A DBMS communication module is included to transmit the data call between the client interface and a hierarchical DBMS on a host within the database network. The client interface and hierarchical DBMS are free of user-defined code.

Abstract: A memory including a memory element having islands is provided. The memory has address decoding circuitry and an array of memory plugs. The memory plugs include memory element that have island structures of a first material within the bulk of a second material. The island structures are typically nanoparticles. The memory plugs can be placed in a first resistive state at a first write voltage, placed in a second resistive state at a second write voltage, and have its resistive state determined at a read voltage.

Abstract: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array in order to prevent unselected conductive array lines from floating to an undesired voltage. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.

Abstract: A multilayered conductive memory device capable of storing information individually or as part of an array of memory devices is provided. Boundary control issues at the interface between layers of the device due to the use of incompatible materials can be avoided by intentionally doping the conductive metal oxide layers that are comprised of substantially similar materials. Methods of manufacture are also provided herein.

Abstract: A system for facilitating XML enable IMS transactions includes a generic XML processor inside an IMS connect program to facilitate any TCP/IP clients, including WebSphere and non-WebSphere, to send and receive XML documents to and from existing IMS transaction business logic. Translations between XML documents and IMS transaction message data structures occur within the IMS connect program under an XML task to parse and transform XML requests and responses. Further, the generic XML processor within the IMS connect program can provide data translation for both non-formatted and formatted IMS transactional messages in XML.

Abstract: High density NVRAM. An array of memory cells capable of storing at least a megabit of information, each memory cell including a memory plug that includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage of a first polarity and reversibly switches from the second resistance state to the first resistance state upon application of a second write voltage of polarity opposite to the first polarity.

Abstract: Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a first level and indicative of a second program state when the read current is at a second level. The read current is ineffective to produce a change in program state. A first voltage pulse is used during a first write mode if a change from a second program state to a first program state is desired. A second voltage pulse is used during a second write mode if a change from the first program state to the second program state is desired.

Abstract: A message is received in a first form for communicating with a first DBMS wherein the first form comprises an internet message prefix and a data portion, the internet message prefix comprising routing information for a client. The message is modified into a second form wherein the client routing information is integrated into the data portion of the message and wherein the second form of the message is utilized to communicate with a second DBMS. A result message generated by the second DBMS is received wherein the result message comprises a result data portion, the result data portion including the routing information. The result message is modified to the first form wherein the result message comprises the internet message prefix, the internet message prefix comprising the client routing information obtained from the result data portion. In this manner, the result message may be routed to the client.

Abstract: A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

Abstract: Providing a cross point, memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.