Abstract: Cross point array with fast access time. A cross point array is driven by drivers on a semiconductor substrate. The drivers for either a single-layer cross point array or for the bottom layer of a stacked cross point array can be positioned to improve access time. Specifically, if the x-direction drivers are positioned in the middle of the x-direction conductive array lines and the y-direction drivers are positioned in the middle of the y-direction conductive array lines, the access time will be improved.

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract: A memory array with components that can withstand high temperature fabrication is provided. Some memory materials require high temperature process steps in order to achieve desired properties. During fabrication, a memory material is deposited on structures that may include metal lines and barrier layers. Such structures are then exposed to the high temperature processing steps and should be resistant to such temperatures.

Abstract: Providing a cross point memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.

Abstract: Line drivers that fit within a specified line pitch. One method of placing line drivers completely underneath a cross point array requires splitting the line driver up so that a portion of the line drivers is on a first side of the cross point array and the other portion is on the opposite side. However, using this technique requires that the width of the drivers is no larger than the width of the memory cells that are being driven. This can be accomplished by stacking transistors such that line drivers fit within a specified line pitch, but are as long as is necessary to include all the necessary circuitry.

Abstract: A multi-resistive state element that uses barrier electrodes is provided. If certain materials are used as electrodes, the electrodes can be used for multiple purposes. Oxides and nitrides are especially well suited for acting as a barrier layer, and possibly even an adhesion layer and a sacrificial layer.

Abstract: Cross point memory array using multiple thin films. The invention is a cross point memory array that uses conductive array lines and multiple thin films as a memory plug. The thin films of the memory plug include a memory element and a non-ohmic device. The memory element switches between resistive states upon application of voltage pulses and the non-ohmic device imparts a relatively high resistance to the memory plug upon application of low magnitude voltages.

Abstract: The invention analyzes areas of conditions with an expert knowledge base of rules using plural separate nodes which fire respective rules of said knowledge base, each of said rules upon being fired altering certain of said conditions predicated upon existence of others of said conditions, the invention operating by constructing a P representation of all pairs of said rules which are input dependent or output dependent; constructing a C representation of all pairs of said rules which are communication dependent or input dependent; determining which of the rules are ready to fire by matching the predicate conditions of each rule with the conditions of said set; enabling said node means to simultaneously fire those of the rules ready to fire which are defined by said P representation as being free of input and output dependencies; and communicating from each node enabled by said enabling step the alteration of conditions by the corresponding rule to other nodes whose rules are defined by said C matrix means as b