Abstract: The invention provides a class of photochromic polydiorganosiloxane vinylic crosslinkers. Each of the photochromic polydiorganosiloxane vinylic crosslinkers of the invention comprise (1) a polydiorganosiloxane polymer chain comprising dimethylsiloxane units and photochromic siloxane unit having one methyl substituent and one organic substituent having a photochromic moiety that capable of undergoing a reversible color change upon exposure to UV-irradiation or high-energy-violet light; (2) two terminal ethylenically-unsaturated groups. The invention also provides a soft photochromic contact lens, especially a photochromic silicone hydrogel contact lens, which comprises a crosslinked polymeric material comprising repeating units of at least one of such a class of photochromic polydiorganosiloxane vinylic crosslinkers.

Abstract: A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system.

Abstract: A light emitting diode warning device is provided capable of acting as a roadway warning flare or as a flashing warning marker the device being portable and rechargeable and presenting warning lights in the vertical direction and in the horizontal direction with the horizontal illumination being observable over 360 degrees.

Abstract: A portable apparatus is provided for detecting the presence in a local atmosphere of gases that are hazardous to the health of humans and animals, the detector providing a warning to the operator of the apparatus of the presence of such gases.

Abstract: A safety alert system 10 is provided which allows the user to initiate a series of telephone communications by activating a pre-programmed control hub 12 by signaling the control hub 12 from a remote activation pendant 14 carried by the user to activate the control hub 12 to begin the control hub 12 dialing multiple pre-selected telephone numbers of pre-selected recipients to inform the recipients of the existence of an emergency situation involving the user, the control hub 12 also determining if the telephone communication has been answered and if the telephone communication has been answered by a person and not a mechanical device.

Abstract: A light emitting diode warning device is provided capable of acting as a roadway warning flare or as a flashing warning marker the device being portable and rechargeable and presenting warning lights in the vertical direction and in the horizontal direction with the horizontal illumination being observable over 360 degrees.

Abstract: A surveillance system is provided having a base unit for receiving digital video and audio transmissions from accessory units equipped with a camera having pan and tilt functions, a motion sensor, an intercom, infrared sensors and a doorbell button for contacting the interior of the dwelling a recording feature is provided to both automatically and on demand record video and audio transmissions received by the base unit from the accessory units.

Abstract: A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit and memory requests from other processors are delivered to the memory controller by an interprocessor router. The memory controller allocates the memory requests in a shared buffer using a credit-based allocation scheme. The cache control unit and the interprocessor router are each assigned a number of credits. Each must pay a credit to the memory controller when a request is allocated to the shared buffer. If the number of filled spaces in the shared buffer is below a threshold, the buffer immediately returns the credits to the source from which the credit and memory request arrived.

Abstract: A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor.

Abstract: A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster.

Abstract: A system and method is disclosed for reducing network message passing latency in a distributed multiprocessing computer system that contains a plurality of microprocessors in a computer network, each microprocessor including router logic to route message packets prioritized in importance by the type of message packet, age of the message packet, and the source of the message packet. The microprocessors each include a plurality of network input ports connected to corresponding local arbiters in the router. The local arbiters are each able to select a message packet from the message packets waiting at the associated network input port. Microprocessor input ports and microprocessor output ports in the microprocessor allow the exchange of message packets between hardware functional units in the microprocessor and between the microprocessors. The microprocessor input ports are similarly each coupled to corresponding local arbiters in the router.

Abstract: A system for scan testing a device under test (“DUT”) in which the clock speed of the DUT differs from test equipment. A plurality of scan-flops in the DUT form a scan-wheel, which defines a closed scan path. The Data bits in the scan path are shifted through a scan-wheel controller based on the DUT clock speed, so that a different bit passes through the scan-wheel controller on each clock cycle of the DUT. Test data is only loaded by replacing the data bit as it passes through the controller. The different clock rates of the DUT and the test equipment define a scan wheel ratio, which is used to determine the number of times that the scan-wheel must rotate before all old data bits are unloaded and replaced by newly loaded bits, and which also determines when data bits passing through the controller will be unloaded and replaced.

Abstract: A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster.

Abstract: A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system.

Abstract: A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system.

Abstract: A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor.

Abstract: A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster.

Abstract: A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contains corrupted data. The processor then replaces the corrupted portion with a predetermined bit pattern known or otherwise programmed into all other processors in the system. The predetermined bit pattern indicates that the associated portion of data was corrupted. The processor that detects the error in the message preferably alerts the system that an error has been detected. The message now containing the predetermined bit pattern in place of the corrupted data is retransmitted to another processor. The predetermined bit pattern will indicate that an error in the message was detected by the previous processor.