Patents by Inventor Steve Oliver

Steve Oliver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11712844
    Abstract: The present invention is directed toward an additive manufacturing method for manufacturing silica-based structures that have a low linear cure shrinkage percentage and an ultra-low coefficient of thermal expansion. The structure may be constructed with a powder mixture that contains at least a first set of silica-based particles that are spherical and that have a first size, and a second set of submicron silica-based particles that are jagged, spherical, or both jagged and spherical. The silica-based powder mixture may be combined with a surfactant in order to create a slurry that can be used to create a 3D printed structure that has a low linear cure shrinkage percentage and an ultra-low coefficient of thermal expansion.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: August 1, 2023
    Assignee: Eagle Technology, LLC
    Inventors: Tukaram K. Hatwar, Rebecca Borrelli, Steve Oliver
  • Publication number: 20210402683
    Abstract: The present invention is directed toward an additive manufacturing method for manufacturing silica-based structures that have a low linear cure shrinkage percentage and an ultra-low coefficient of thermal expansion. The structure may be constructed with a powder mixture that contains at least a first set of silica-based particles that are spherical and that have a first size, and a second set of submicron silica-based particles that are jagged, spherical, or both jagged and spherical. The silica-based powder mixture may be combined with a surfactant in order to create a slurry that can be used to create a 3D printed structure that has a low linear cure shrinkage percentage and an ultra-low coefficient of thermal expansion.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Inventors: Tukaram K. HATWAR, Rebecca BORRELLI, Steve OLIVER
  • Patent number: 9966406
    Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Publication number: 20170040375
    Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings.
    Type: Application
    Filed: October 20, 2016
    Publication date: February 9, 2017
    Inventors: Kyle K. Kirby, Steve Oliver
  • Patent number: 9484378
    Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: November 1, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Patent number: 8982469
    Abstract: A method and apparatus providing a lens master device and use of the same to form a lens template and/or a lens structure. The method includes obtaining a plurality of individual lens masters, each of which has a shaped portion defining at least a portion of a lens structure to be formed. The lens masters are affixed onto a supporting structure to form a lens master device.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Steve Oliver
  • Patent number: 8963292
    Abstract: Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Steve Oliver, Warren Farnworth
  • Publication number: 20140191303
    Abstract: Semiconductor devices may include a semiconductor substrate comprising at least one of transistors and capacitors may be located at an active surface of the semiconductor substrate. An imperforate dielectric material may be located on the active surface, the imperforate dielectric material covering the at least one of transistors and the capacitors. Electrically conductive material in contact openings may be electrically connected to the at least one of transistors and capacitors and extend to a back side surface of the semiconductor substrate. Laterally extending conductive elements may extend over the back side surface of the semiconductor substrate and may be electrically connected to the conductive material in the contact openings.
    Type: Application
    Filed: March 13, 2014
    Publication date: July 10, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Patent number: 8679933
    Abstract: Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Patent number: 8680634
    Abstract: Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Swarnal Borthakur, Rick Lake, Andy Perkins, Scott Churchwell, Steve Oliver
  • Publication number: 20130330922
    Abstract: The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Steve Oliver, Warren M. Farnworth
  • Patent number: 8531046
    Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Kyle K. Kirby, Steve Oliver, Mark Hiatt
  • Patent number: 8395242
    Abstract: Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: March 12, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Steve Oliver, Warren Farnworth
  • Patent number: 8294273
    Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: October 23, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, William Mark Hiatt, Steve Oliver, Alan G. Wood, Sidney B. Rigg, James M. Wark, Kyle K. Kirby
  • Publication number: 20110287572
    Abstract: Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices.
    Type: Application
    Filed: August 4, 2011
    Publication date: November 24, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Patent number: 8048708
    Abstract: Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: November 1, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Swarnal Borthakur, Rick Lake, Andy Perkins, Scott Churchwell, Steve Oliver
  • Patent number: 8017982
    Abstract: Methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating image sensing elements, transistors, and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Imagers with image sensing elements and transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such imagers.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: September 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kyle K. Kirby, Steve Oliver
  • Publication number: 20110204462
    Abstract: Method and apparatus providing a wafer level fabrication of imager modules in which a permanent carrier protects imager devices on an imager wafer and is used to support a lens wafer.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Inventors: Swarnal Borthakur, Rick Lake, Andy Perkins, Scott Churchwell, Steve Oliver
  • Publication number: 20110204526
    Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined.
    Type: Application
    Filed: May 3, 2011
    Publication date: August 25, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Dave Pratt, Kyle Kirby, Steve Oliver, Mark Hiatt
  • Publication number: 20110169122
    Abstract: Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment includes providing a substrate comprising a via formed therein. The substrate has a front side and a backside. The embodiment may further include forming a trench on the backside of the substrate, disposing an insulating material in the trench, and forming a trace over the insulating material in the trench.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Steve Oliver, Warren Farnworth