Abstract: Circuitry for locking out a first signal generated from a first power supply while the first power supply is at or below a first voltage level is described for a non-volatile semiconductor memory. The circuitry includes a first P-type transistor P1 having a gate, a drain, and a source. The source of P1 is coupled to a second power supply, the drain of P1 is coupled to a first node and the gate of P1 is coupled to a second node. The second node provides an output signal representative of the first control signal. The circuitry also includes a first N-type transistor N1, having a gate, a drain, and a source. The drain of N1 is coupled to the first node, the source of N1 is coupled to a third, and the gate of N1 is coupled to the first control signal and to a fourth node. Included is a second N-type transistor N2, having a drain, a source and a gate. The gate of N2 is coupled a sixth node. The drain of N2 is coupled to the second node and the source of N2 is coupled to the third node.