Patents by Inventor Steven Alfred Kummerl
Steven Alfred Kummerl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200211959Abstract: An integrated circuit (IC) package comprises a semiconductor die, a leadframe comprising a plurality of leads coupled to bond pads on the semiconductor die, and an electrically conductive member electrically coupled to the leadframe. A magnetic mold compound encapsulates the electrically conductive member to form an inductor. A non-magnetic mold compound encapsulates the semiconductor die, the leadframe, and the magnetic mold compound.Type: ApplicationFiled: December 26, 2018Publication date: July 2, 2020Inventors: Dongbin HOU, Steven Alfred KUMMERL, Roberto Giampiero MASSOLINI, Joyce Marie MULLENIX
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Patent number: 10553573Abstract: Integrated circuits may be assembled by placing a batch of integrated circuit (IC) die on a leadframe. Each of the IC die includes a magnetically responsive structure that may be an inherent part of the IC die or may be explicitly added. The IC die are then agitated to cause the IC die to move around on the leadframe. The IC die are captured in specific locations on the leadframe by an array of magnetic domains that produce a magnetic response from the plurality of IC die. The magnetic domains may be formed on the lead frame, or may be provided by a magnetic chuck positioned adjacent the leadframe.Type: GrantFiled: September 1, 2017Date of Patent: February 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Daniel Lee Revier, Steven Alfred Kummerl, Benjamin Stassen Cook
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Publication number: 20190355652Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.Type: ApplicationFiled: November 30, 2018Publication date: November 21, 2019Inventors: Hung-Yu CHOU, Bo-Hsun PAN, Yuh-Harng CHIEN, Fu-Hua YU, Steven Alfred KUMMERL, Jie CHEN, Rajen M. MURUGAN
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Publication number: 20190326131Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Yuh-Harng CHIEN, Hung-Yu CHOU, Fu-Kang LEE, Steven Alfred KUMMERL
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Publication number: 20190206699Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.Type: ApplicationFiled: December 29, 2017Publication date: July 4, 2019Inventors: Yuh-Harng CHIEN, Hung-Yu CHOU, Fu-Kang LEE, Steven Alfred KUMMERL
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Patent number: 10340152Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.Type: GrantFiled: December 29, 2017Date of Patent: July 2, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yuh-Harng Chien, Hung-Yu Chou, Fu-Kang Lee, Steven Alfred Kummerl
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Publication number: 20190139868Abstract: Semiconductor devices and methods and apparatus to produce such semiconductor devices are disclosed. An integrated circuit package includes a lead frame including a die attach pad and a plurality of leads; a die including a MEMs region defined by a plurality of trenches, the die electrically connected to the plurality of leads; and a mold compound covering portions of the die, the mold compound defining a cavity between a surface of the die and a surface of the mold compound, wherein the mold compound defines a vent.Type: ApplicationFiled: November 9, 2017Publication date: May 9, 2019Inventors: Robert Allan Neidorff, Benjamin Cook, Steven Alfred Kummerl, Barry Jon Male, Peter Smeys
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Publication number: 20190074270Abstract: Integrated circuits may be assembled by placing a batch of integrated circuit (IC) die on a leadframe. Each of the IC die includes a magnetically responsive structure that may be an inherent part of the IC die or may be explicitly added. The IC die are then agitated to cause the IC die to move around on the leadframe. The IC die are captured in specific locations on the leadframe by an array of magnetic domains that produce a magnetic response from the plurality of IC die. The magnetic domains may be formed on the lead frame, or may be provided by a magnetic chuck positioned adjacent the leadframe.Type: ApplicationFiled: September 1, 2017Publication date: March 7, 2019Inventors: Daniel Lee Revier, Steven Alfred Kummerl, Benjamin Stassen Cook
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Patent number: 9679864Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.Type: GrantFiled: October 13, 2016Date of Patent: June 13, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Juan Alejandro Herbsommer, Matthew David Romig, Steven Alfred Kummerl, Wei-Yan Shih
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Patent number: 9646906Abstract: A method forming packaged semiconductor devices includes providing a completed semiconductor package having a die with bond pads coupled to package pins. Sensor precursors including an ink and a liquid carrier are additively printed directly on the die or package to provide precursors for electrodes and a sensing material between the sensor electrodes. Sintering or curing removes the liquid carrier such that an ink residue remains to provide the sensor electrodes and sensing material. The sensor electrodes electrically coupled to the pins or bond pads or the die includes a wireless coupling structure coupled to the bond pads and the method includes additively printing an ink then sintering or curing to form a complementary wireless coupling structure on the completed semiconductor package coupled to the sensor electrodes so that sensing signals sensed by the sensor are wirelessly transmitted to the bond pads after being received by the wireless coupling structure.Type: GrantFiled: September 9, 2015Date of Patent: May 9, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Juan Alejandro Herbsommer, Django Trombley, Steven Alfred Kummerl, Paul Emerson
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Publication number: 20170033072Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.Type: ApplicationFiled: October 13, 2016Publication date: February 2, 2017Inventors: Benjamin Stassen Cook, Juan Alejandro Herbsommer, Matthew David Romig, Steven Alfred Kummerl, Wei-Yan Shih
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Patent number: 9496171Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.Type: GrantFiled: September 9, 2015Date of Patent: November 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benjamin Stassen Cook, Juan Alejandro Herbsommer, Matthew David Romig, Steven Alfred Kummerl, Wei-Yan Shih
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Publication number: 20160093548Abstract: A method forming packaged semiconductor devices includes providing a completed semiconductor package having a die with bond pads coupled to package pins. Sensor precursors including an ink and a liquid carrier are additively printed directly on the die or package to provide precursors for electrodes and a sensing material between the sensor electrodes. Sintering or curing removes the liquid carrier such that an ink residue remains to provide the sensor electrodes and sensing material. The sensor electrodes electrically coupled to the pins or bond pads or the die includes a wireless coupling structure coupled to the bond pads and the method includes additively printing an ink then sintering or curing to form a complementary wireless coupling structure on the completed semiconductor package coupled to the sensor electrodes so that sensing signals sensed by the sensor are wirelessly transmitted to the bond pads after being received by the wireless coupling structure.Type: ApplicationFiled: September 9, 2015Publication date: March 31, 2016Inventors: BENJAMIN STASSEN COOK, JUAN ALEJANDRO HERBSOMMER, DJANGO TROMBLEY, STEVEN ALFRED KUMMERL, PAUL EMERSON
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Publication number: 20160093525Abstract: A method forming a packaged semiconductor device includes providing a first semiconductor die (first die) having bond pads thereon mounted face-up on a package substrate or on a die pad of a lead frame (substrate), wherein the substrate includes terminals or contact pads (substrate pads). A first dielectric layer is formed including printing a first dielectric precursor layer including a first ink having a first liquid carrier solvent extending from the substrate pads to the bond pads. A first interconnect precursor layer is printed including a second ink having a second liquid carrier over the first dielectric layer extending from the substrate pads to the bond pads. Sintering or curing the first interconnect precursor layer removes at least the second liquid carrier to form an electrically conductive interconnect including an ink residue which connects respective substrate pads to respective bond pads.Type: ApplicationFiled: September 9, 2015Publication date: March 31, 2016Inventors: BENJAMIN STASSEN COOK, JUAN ALEJANDRO HERBSOMMER, MATTHEW DAVID ROMIG, STEVEN ALFRED KUMMERL, WEI-YAN SHIH
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Publication number: 20150105630Abstract: A heart pulse monitor includes a permanent magnet including a mounting structure for securing the permanent magnet in displaceable contact with a blood vessel of a wearer. The permanent magnet has a thickness defining an axial direction that the permanent magnet is displaceable when blood flows. A fluxgate sensor system is positioned a distance in the axial direction from the permanent magnet to sense an axial magnetic field therefrom. The permanent magnet displaces in the axial direction upon a heart pulse of the wearer resulting in a change in the axial magnetic field which is sensed by the fluxgate sensor system through a change in an induced AC output signal on the sense coil. A processor is coupled to receive information from the induced AC output signal. The processor implements calibration data which converts information from the induced AC output signal into a heart pulse measurement for the wearer.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Inventors: STEVEN ALFRED KUMMERL, ANURAAG MOHAN, VIOLA SCHAFFER
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Publication number: 20110012243Abstract: A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413).Type: ApplicationFiled: September 23, 2010Publication date: January 20, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Kapil Heramb SAHASRABUDHE, Steven Alfred KUMMERL
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Patent number: 7821113Abstract: A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413).Type: GrantFiled: June 3, 2008Date of Patent: October 26, 2010Assignee: Texas Instruments IncorporatedInventors: Kapil Heramb Sahasrabudhe, Steven Alfred Kummerl
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Publication number: 20090294932Abstract: A lead frame (410) including a die pad (100) for mounting at least one integrated circuit (405) thereon and a plurality of lead fingers (413). The die pad (100) includes a metal including substrate (105) having a periphery that includes a plurality of sides (111-114), an intersection of the sides forming corners (115). A first plurality of grooves including least one groove (106) is formed in a top side surface of the substrate and is associated with each of the corners (115). The groove (106) has a dimension oriented at least in part at an angle of 75 to 105 degrees relative to a bisecting line (118) originating from the corners (115). A lead-frame-based packaged semiconductor device (400) includes a lead frame (410) including at least one metal comprising die pad (418) and a plurality of lead fingers (413) around the die pad (418). At least one integrated circuit (405) is mounted on the top surface of the die pad (418), and electrically connected to the plurality of lead fingers (413).Type: ApplicationFiled: June 3, 2008Publication date: December 3, 2009Inventors: Kapil Heramb Sahasrabudhe, Steven Alfred Kummerl
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Patent number: 7504713Abstract: A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent lands have their facing parallel perimeter portions oriented in parallel, defining a centerline. The land perimeters have flanges remote from the surface, each flange shaped by an outline. For adjacent lands, the flanges (207b, 218, 219) of the parallel perimeter portions have asymmetrical outlines relative to the centerline and are in concord so that alternately the flange of one land diminishes its outline where the flange of the adjacent land protrudes its outline. This coordinated variation shapes the space between the adjacent flanges in a meander-like mode. Adhesive plastic material is anchored in the space to hinder a land shift along the parallel perimeter portions.Type: GrantFiled: January 16, 2007Date of Patent: March 17, 2009Assignee: Texas Instruments IncorporatedInventors: Jeffrey Gail Holloway, Steven Alfred Kummerl
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Publication number: 20080169554Abstract: A semiconductor device having a plastic package with a linear array of metal lands (202, 212) with parallel perimeter portions (203a, 213a). Pairs of adjacent lands have their facing parallel perimeter portions oriented in parallel, defining a centerline. The land perimeters have flanges remote from the surface, each flange shaped by an outline. For adjacent lands, the flanges (207b, 218, 219) of the parallel perimeter portions have asymmetrical outlines relative to the centerline and are in concord so that alternately the flange of one land diminishes its outline where the flange of the adjacent land protrudes its outline. This coordinated variation shapes the space between the adjacent flanges in a meander-like mode. Adhesive plastic material is anchored in the space to hinder a land shift along the parallel perimeter portions.Type: ApplicationFiled: January 16, 2007Publication date: July 17, 2008Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Jeffrey Gail Holloway, Steven Alfred Kummerl