Patents by Inventor Steven C. Bartling
Steven C. Bartling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11393971Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.Type: GrantFiled: November 27, 2018Date of Patent: July 19, 2022Assignee: Texas Instruments IncorporatedInventors: Sudhanshu Khanna, Michael Zwerg, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Publication number: 20210389174Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: ApplicationFiled: August 31, 2021Publication date: December 16, 2021Inventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Patent number: 11105676Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: GrantFiled: November 14, 2018Date of Patent: August 31, 2021Assignee: Texas Instruments IncorporatedInventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Patent number: 10873020Abstract: A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.Type: GrantFiled: August 8, 2017Date of Patent: December 22, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Wei-Yan Shih, Sudhanshu Khanna, Michael Zwerg, Juergen Luebbe, Gregory Allen North, Steven C. Bartling, Leah Trautmann, Scott Robert Summerfelt
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Patent number: 10734978Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.Type: GrantFiled: December 28, 2018Date of Patent: August 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Soman Purushothaman, Sankar Prasad Debnath, Per Torstein Roine, Steven C. Bartling, Keshav Bhaktavatson Chintamani
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Publication number: 20200212896Abstract: In described examples, a latch includes circuitry for latching input information. The circuitry can be precharged in response to an indication of a first mode and can latch the input information to an indication of a second mode. The latch can optionally further latch the input information in response to a node for storing the latched input information.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Soman Purushothaman, Sankar Prasad Debnath, Per Torstein Roine, Steven C. Bartling, Keshav Bhaktavatson Chintamani
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Publication number: 20200168786Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.Type: ApplicationFiled: November 27, 2018Publication date: May 28, 2020Inventors: Sudhanshu Khanna, Michael Zwerg, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Publication number: 20190162590Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: ApplicationFiled: November 14, 2018Publication date: May 30, 2019Inventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
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Publication number: 20190051812Abstract: A piezoelectric sensor with: (i) a capacitive element, comprising piezoelectric material; (ii) a pre-conditioning circuit, comprising circuitry for establishing a polarization of the capacitive element in a polarizing mode; and (iii) signal amplification circuitry for providing a piezoelectric-responsive output signal, in response to charge across the capacitive element in a sensing mode.Type: ApplicationFiled: August 8, 2017Publication date: February 14, 2019Inventors: Wei-Yan Shih, Sudhanshu Khanna, Michael Zwerg, Juergen Luebbe, Gregory Allen North, Steven C. Bartling, Leah Trautmann, Scott Robert Summerfelt
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Patent number: 9520862Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: GrantFiled: July 31, 2014Date of Patent: December 13, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven C. Bartling, Sudhanshu Khanna
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Patent number: 9520863Abstract: In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: GrantFiled: July 31, 2014Date of Patent: December 13, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven C. Bartling, Sudhanshu Khanna
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Patent number: 9018976Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: GrantFiled: November 14, 2013Date of Patent: April 28, 2015Assignee: Texas Instruments IncorporatedInventors: Steven C. Bartling, Sudhanshu Khanna
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Patent number: 9007091Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: GrantFiled: November 14, 2013Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Steven C. Bartling, Sudhanshu Khanna
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Publication number: 20150070061Abstract: In an embodiment of the invention, a dual-port negative level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: ApplicationFiled: July 31, 2014Publication date: March 12, 2015Applicant: Texas Instruments IncorporatedInventors: Steven C. Bartling, Sudhanshu Khanna
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Publication number: 20150054557Abstract: In an embodiment of the invention, a dual-port negative level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: ApplicationFiled: July 31, 2014Publication date: February 26, 2015Applicant: Texas Instruments IncorporatedInventors: Steven C. Bartling, Sudhanshu Khanna
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Publication number: 20150054545Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low, rest control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: ApplicationFiled: November 14, 2013Publication date: February 26, 2015Inventors: Steven C. Bartling, Sudhanshu Khanna
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Publication number: 20150054544Abstract: In an embodiment of the invention, a dual-port positive level sensitive preset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, preset control signal PRE is low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signals RET and RETN, the preset control signal PRE and the control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, PRE, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signals RET and RETN determine when data is stored in the dual-port latch during retention mode.Type: ApplicationFiled: November 14, 2013Publication date: February 26, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven C. Bartling, Sudhanshu Khanna
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Patent number: 8692592Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.Type: GrantFiled: June 30, 2005Date of Patent: April 8, 2014Assignee: Texas Instruments IncorporatedInventors: Charles M. Branch, Steven C. Bartling, Dharin N. Shah
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Patent number: 7908535Abstract: Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.Type: GrantFiled: June 30, 2009Date of Patent: March 15, 2011Assignee: Texas Instruments IncorporatedInventors: Charles M. Branch, Steven C. Bartling
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Publication number: 20100332929Abstract: Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.Type: ApplicationFiled: June 30, 2009Publication date: December 30, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Charles M. Branch, Steven C. Bartling