Patents by Inventor Steven C. Miller
Steven C. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110016277Abstract: In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Each of the plurality of coherency protocols has a unique set of cache states that may be applied to cached data for the first memory transaction. Cache coherency is performed on appropriate caches in the computing system by applying the set of cache states of the selected one of the plurality of coherency protocols.Type: ApplicationFiled: September 21, 2010Publication date: January 20, 2011Inventors: Steven C. Miller, Martin M. Deneroff, Kenneth C. Yeager
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Patent number: 7873741Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: GrantFiled: November 4, 2008Date of Patent: January 18, 2011Assignee: Silicon Graphics InternationalInventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Publication number: 20100281207Abstract: A flash-based data archive storage system having a large capacity storage array constructed from a plurality of dense flash devices is provided. The flash devices are illustratively multi-level cell (MLC) flash devices that are tightly packaged to provide a low-power, high-performance data archive system having substantially more capacity per cubic inch than more dense tape or disk drives. The flash-based data archive system may be adapted to employ conventional data de-duplication and compression methods to compactly store data. Furthermore, the flash-based archive system has a smaller footprint and consumes less power than the tape and/or disk archive system.Type: ApplicationFiled: April 5, 2010Publication date: November 4, 2010Inventors: Steven C. Miller, Don Trimmer, Steven R. Kleiman
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Patent number: 7806827Abstract: An ultrasound breast imaging assembly includes first and second compression plates angled with respect to one another, a breast compression area defined between the first and second compression plates, at least one pivot assembly, and an ultrasound probe. The pivot assembly allows relative motion between the first and second compression plates. The ultrasound probe, which is configured to translate over one of the first and second compression plates, includes an active matrix array (AMA) positioned on one of the first and second compression plates.Type: GrantFiled: July 9, 2003Date of Patent: October 5, 2010Assignee: General Electric CompanyInventors: Heidi D. Zhang, Robert F. Lawrence, Gilbert M. Lima, Steven C. Miller, Anne L. Hall
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Patent number: 7802058Abstract: In a computing system, cache coherency is performed by selecting one of a plurality of coherency protocols for a first memory transaction. Cache coherency is performed on appropriate caches in the computing system in accordance with the selected one of the plurality of coherency protocols. For a second memory transaction, another selection is made of the plurality of coherency protocols. The selected one of the coherency protocols for the second memory transaction may be the same as or different from the selected one of the plurality of coherency protocols for the first memory transaction.Type: GrantFiled: April 30, 2004Date of Patent: September 21, 2010Assignee: Silicon Graphics InternationalInventors: Steven C. Miller, Martin M. Deneroff, Kenneth C. Yeager
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Publication number: 20100204580Abstract: An ultrasound breast imaging assembly includes first and second compression plates angled with respect to one another, a breast compression area defined between the first and second compression plates, at least one pivot assembly, and an ultrasound probe. The pivot assembly allows relative motion between the first and second compression plates. The ultrasound probe, which is configured to translate over one of the first and second compression plates, includes an active matrix array (AMA) positioned on one of the first and second compression plates.Type: ApplicationFiled: April 16, 2010Publication date: August 12, 2010Inventors: Heidi D. Zhang, Robert F. Lawrence, Gilbert M. Lima, Steven C. Miller, Anne L. Hall
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Patent number: 7712006Abstract: A system for conveying information includes a signal transport device. The signal transport device includes a set of links operable to convey a first set of information signals from a first computer module to a second computer module and a link operable to convey a transaction request credit signal associated with the first set of information signals, the signal indicating whether at least a portion of a transaction request message may be sent using the first set of information signals. The device also includes a set of links operable to convey a second set of information signals in the opposite direction of the first set of information signals and a link operable to convey a transaction request credit signal associated with the second set of information signals, the signal indicating whether at least a portion of a transaction request message may be sent using the second set of information signals.Type: GrantFiled: December 4, 2002Date of Patent: May 4, 2010Assignee: Silicon Graphics InternationalInventor: Steven C. Miller
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Publication number: 20100083247Abstract: A processing system includes a plurality of virtual machines which have shared access to a non-volatile solid-state memory (NVSSM) subsystem, by using remote direct memory access (RDMA). The NVSSM subsystem can include flash memory and other types of non-volatile solid-state memory. The processing system uses scatter-gather lists to specify the RDMA read and write operations. Multiple reads or writes can be combined into a single RDMA read or write, respectively, which can then be decomposed and executed as multiple reads or writes, respectively, in the NVSSM subsystem. Memory accesses generated by a single RDMA read or write may be directed to different memory devices in the NVSSM subsystem, which may include different forms of non-volatile solid-state memory.Type: ApplicationFiled: September 26, 2008Publication date: April 1, 2010Applicant: NetApp, Inc.Inventors: Arkady Kanevsky, Steven C. Miller
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Patent number: 7674588Abstract: Methods and apparatus are described for detecting specific binding between first and second chemical entities. The first chemical entity in association with a first fluorophore is immobilized. The second chemical entity is allowed to bind with the immobilized first chemical entity. The second chemical entity is or becomes coupled to a second fluorophore, which forms a FRET pair with the first fluorophore. The bound chemical entities are exposed to radiation at an excitation frequency for either the first or the second fluorophore, and polarization anisotropy of a FRET fluorescent signal from the bound chemical entities is measured to detect specific binding between the first and second chemical entities.Type: GrantFiled: February 11, 2008Date of Patent: March 9, 2010Assignee: Blueshift Biotechnologies, Inc.Inventors: Steven C. Miller, Paul B. Comita, Christopher B. Shumate, Evan F. Cromwell
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Patent number: 7643146Abstract: Methods and apparatus for performing scatterometry measurements of biological samples as described herein. A substrate having formed therein one or more sample wells is provided. Each sample well is configured to hold a sample solution containing objects that are to be characterized based on their light scattering properties. One or more sample solutions are dispensed into the sample wells. A specular reflection reducing element is applied to at least some of the sample solutions in the sample wells to decrease reflections of light into one or more detectors. A light beam is directed from a light source onto the objects in the sample wells. Light scattered by the objects in the sample wells is collected and transmitted to one or more detectors. The signal from the detectors is analyzed to detect the one or more characteristics of the one or more samples.Type: GrantFiled: January 20, 2006Date of Patent: January 5, 2010Assignee: Blueshift Biotechnologies, Inc.Inventors: Evan F. Cromwell, Steven C. Miller, Robert T. Trujillo, Paul B. Comita
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Publication number: 20090070480Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: ApplicationFiled: November 4, 2008Publication date: March 12, 2009Applicant: Silicon Graphis, Inc.Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Publication number: 20080301134Abstract: A sampling based technique for eliminating duplicate data (de-duplication) stored on storage resources, is provided. According to the invention, when a new data set, e.g., a backup data stream, is received by a server, e.g., a storage system or virtual tape library (VTL) system implementing the invention, one or more anchors are identified within the new data set. The anchors are identified using a novel anchor detection circuitry in accordance with an illustrative embodiment of the present invention. Upon receipt of the new data set by, for example, a network adapter of a VTL system, the data set is transferred using direct memory access (DMA) operations to a memory associated with an anchor detection hardware card that is operatively interconnected with the storage system. The anchor detection hardware card may be implemented as, for example, a FPGA is to quickly identify anchors within the data set.Type: ApplicationFiled: May 31, 2007Publication date: December 4, 2008Inventors: Steven C. Miller, Roger Stager
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Patent number: 7453878Abstract: A multiple channel data transfer system (10) includes a source (12) that generates data packets with sequence numbers for transfer over multiple request channels (14). Data packets are transferred over the multiple request channels (14) through a network (16) to a destination (18). The destination (18) re-orders the data packets received over the multiple request channels (14) into a proper sequence in response to the sequence numbers to facilitate data processing. The destination (18) provides appropriate reply packets to the source (12) over multiple response channels (20) to control the flow of data packets from the source (12).Type: GrantFiled: July 20, 2001Date of Patent: November 18, 2008Assignee: Silicon Graphics, Inc.Inventors: Randal G. Martin, Steven C. Miller, Mark D. Stadler, David A. Kruckemyer
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Patent number: 7447794Abstract: A system and method for conveying data include the capability to determine whether a transaction request credit has been received at a computer module, the transaction request credit indicating that at least a portion of a transaction request message may be sent. The system and method also include the capability to determine, if a transaction request message is to be sent, whether at least a portion of the transaction request message may be sent and to send the at least a portion of the transaction request message if it may be sent.Type: GrantFiled: December 4, 2002Date of Patent: November 4, 2008Assignee: Silicon Graphics, Inc.Inventors: Steven C. Miller, Thomas Edward McGee, Bruce Alan Strangfeld
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Publication number: 20080263384Abstract: A system and method for prioritization of clock rates in a multi-core processor is provided. Instruction arrival rates are measured during a time interval Ti?1 to Ti by a monitoring module either internal to the processor or operatively interconnected with the processor. Using the measured instruction arrival rates, the monitoring module calculates an optimal instruction arrival rate for each core of the processor. For processors that support continuous frequency changes for cores, each core is then set to an optimal service rate. For processors that only support a discrete set of arrival rates, the optimal rates are mapped to a closest supported rate and the cores are set to the closest supported rate. This procedure is then repeated for each time interval.Type: ApplicationFiled: April 23, 2007Publication date: October 23, 2008Inventors: Steven C. Miller, Naresh Patel
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Publication number: 20080206888Abstract: Methods and apparatus are described for detecting specific binding between first and second chemical entities. The first chemical entity in association with a first fluorophore is immobilized. The second chemical entity is allowed to bind with the immobilized first chemical entity. The second chemical entity is or becomes coupled to a second fluorophore, which forms a FRET pair with the first fluorophore. The bound chemical entities are exposed to radiation at an excitation frequency for either the first or the second fluorophore, and polarization anisotropy of a FRET fluorescent signal from the bound chemical entities is measured to detect specific binding between the first and second chemical entities.Type: ApplicationFiled: February 11, 2008Publication date: August 28, 2008Inventors: Steven C. Miller, Paul B. Comita, Christopher B. Shumate, Evan F. Cromwell
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Patent number: 7398359Abstract: A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.Type: GrantFiled: April 30, 2004Date of Patent: July 8, 2008Assignee: Silicon Graphics, Inc.Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, Larry Rudolph, Charles E. Leiserson, Bradley C. Kuszmaul, Krste Asanovic
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Patent number: 7197589Abstract: A computer system (10) includes a bus controller (12), a bus (14), a plurality of processing devices (16) and a plurality of enabling switches (18). Each enabling switch (18) corresponds to a separate one of the processing devices (16). Each processing device (16) sends an access request (24) to arbitration logic (22) in the bus controller (12), requesting access to the bus (14). The arbitration logic (22) selects one of the access requests (24) according to a priority protocol. The arbitration logic (22) generates a control signal (20) associated with the selected access request (24). The control signal (20) is provided to the enabling switch (18) corresponding to the processing device (16) that sent the selected access request (24). The enabling switch (18) enables access to the bus (14) for the processing device (16) in response to the control signal (20).Type: GrantFiled: May 21, 1999Date of Patent: March 27, 2007Assignee: Silicon Graphics, Inc.Inventors: Martin M. Deneroff, Steven C. Miller
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Patent number: 7181589Abstract: An address translation unit generates a physical address for access to a memory from a virtual address using either a translation lookaside buffer or a segmentation buffer. If the virtual address falls within a predetermined range, the address translation unit will use the segmentation buffer to generate the physical address. Upon generation of the physical address, the memory will either receive data from or provide data to a processor in accordance with the instructions being processed by the processor.Type: GrantFiled: April 30, 2004Date of Patent: February 20, 2007Assignee: Silicon Graphics, Inc.Inventors: Steven C. Miller, Martin M. Deneroff, Curt F. Schimmel, John Carter, Lixin Zhang, Michael Parker
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Patent number: 7141378Abstract: Methods, apparatus, and system, implementing and using techniques for detecting a presence of one or more target analytes in particular regions of interest of one or more samples. One or more samples including objects and one or more target analytes are provided. Some of the target analytes are labeled with a fluorophore and are bound to some of the objects in the samples. The samples are illuminated with fluorescence inducing light and fluorescent light is collected from one or more regions of the one or more samples. At least one anisotropy measurement of the samples is performed to identify regions of interest where one or more target analytes are bound to the objects. The collected fluorescent light from the regions of interest is analyzed to determine a presence of target analytes that are bound to the objects in the one or more samples.Type: GrantFiled: July 1, 2005Date of Patent: November 28, 2006Assignee: Blueshift Biotechnologies, Inc.Inventors: Steven C. Miller, Paul B. Comita, Evan F. Cromwell, Christopher B. Shumate