Abstract: A data processing system includes a memory controller which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

Abstract: A data processing system 2 includes a memory controller 20 which dynamically selects from a plurality of candidate management algorithms a selected management algorithm to be used for managing memory access conflicts. The memory management algorithms may include various versions of speculative memory access issue and/or memory access issue using memory locks. The dynamic selection is performed on the basis of detected state parameters of the system. These detected state parameters may include conflict level indicators, such as memory access conflict counters tracked on one or more of a global, per-process, per-region or per-thread basis.

Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.

Abstract: A caching circuit includes tag memories for storing tagged addresses of a first cache. On-chip data memories are arranged in the same die as the tag memories, and the on-chip data memories form a first sub-hierarchy of the first cache. Off-chip data memories are arranged in a different die as the tag memories, and the off-chip data memories form a second sub-hierarchy of the first cache. Sources (such as processors) are arranged to use the tag memories to service first cache requests using the first and second sub-hierarchies of the first cache.

Abstract: In accordance with at least some embodiments, a digital signal processor (DSP) includes an instruction fetch unit and an instruction decode unit in communication with the instruction fetch unit. The DSP also includes a register set and a plurality of work units in communication with the instruction decode unit. The register set includes a plurality of legacy predicate registers. Separate from the legacy predicate registers, a plurality of on-demand predicate registers are selectively signaled without changing the opcode space for the DSP.

Abstract: A method and apparatus is provided for operating a digital system having several processors (102, 104) and peripheral devices (106, 116) connected to a shared memory subsystem (112). Two or more of the processors execute separate operating systems. In order to control access to shared resources, a set of address space regions within an address space of the memory subsystem is defined within system protection map (SPM) (150). Resource access rights are assigned to at least a portion of the set of regions to indicate which initiator resource is allowed to access each region. Using the address provided with the access request, the region being accessed by a memory access request is identified by the SPM. During each access request, the SPM identifies the source of the request using a resource identification value (R-ID) provided with each access request and then a determination is made of whether the resource accessing the identified region has access rights for the identified region.

Abstract: A digital system is provided with a microprocessor (100), a cache (120) and various memory and devices (140a-140n). Signals to control certain cache memory modes are provided by a physical address attribute memory (PAAM) (130). For devices present in the address space of the digital system that have different capabilities and characteristics, misuse is prevented by signaling an error or otherwise limiting the use of each device in response to attribute bits in the PAAM associated with the memory mapped address of the device. A memory management unit (110) with address translation capabilities and/or memory protection features may also be present, but is not required for operation of the PAAM.

Abstract: A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog, a kernel, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline loop procedure can be terminated early. A second software pipeline loop procedure can be initiated prior to the completion of first software pipeline loop procedure.

Abstract: A data processing system (1300) is provided with a digital signal processor (DSP) (1301) that has an instruction set architecture (ISA) that is optimized for intensive numeric algorithm processing. The DSP has dual load/store units (.D1, .D2) connected to dual memory ports (T1, T2) in a level one data cache memory controller (1720a). The DSP can execute two aligned data transfers each having a length of one byte, two bytes, four bytes, or eight bytes in parallel by executing two load/store instructions. The DSP can also execute a single non-aligned data transfer having a length of four bytes or eight bytes by executing a non-aligned load/store instruction that utilizes both memory target ports.

Abstract: A method and apparatus is provided for operating a digital system having several processors (102, 104) and peripheral devices (106, 116) connected to a shared memory subsystem (112). Two or more of the processors execute separate operating systems. In order to control access to shared resources, a set of address space regions within an address space of the memory subsystem is defined within system protection map (SPM) (150). Resource access rights are assigned to at least a portion of the set of regions to indicate which initiator resource is allowed to access each region. Using the address provided with the access request, the region being accessed by a memory access request is identified by the SPM. During each access request, the SPM identifies the source of the request using a resource identification value (R-ID) provided with each access request and then a determination is made of whether the resource accessing the identified region has access rights for the identified region.

Abstract: A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

Abstract: A microprocessor (12) comprising a cache circuit (20) and circuitry (46, 48, 41, 56) for issuing a prefetch request. The prefetch request (82) comprises an address (82a) and requests information of a first size (82b) from the cache circuit. The microprocessor also includes prefetch control circuitry (22), which comprises circuitry for receiving the prefetch request and evaluation circuitry for evaluating system parameters corresponding to the prefetch request. Additionally, the prefetch control circuitry comprises circuitry, responsive to the evaluation circuitry, for determining a size of information for a prefetch operation starting at the address from the cache circuit, where the prefetch operation corresponds to the prefetch request.

Abstract: A microprocessor (5) for coupling to an external read/write memory (20) having an addressable storage space. This storage space stores cacheable digital data and non-cacheable (32) digital data. The microprocessor includes a data storage circuit (62) for storing a portion of the non-cacheable data. The microprocessor further includes an address storage circuit (64) for storing an address corresponding to the portion of the non-cacheable data. Still further, the microprocessor includes a counter (72) for advancing a count from an initial value (74) toward a threshold value (76) in response to an activity over time. The counter initiates its advancing operation in response to the data storage circuit receiving the portion of the non-cacheable data. Lastly, the microprocessor includes an indicator (66) for indicating the portion of the non-cacheable data in the data storage circuit is expired in response to the count reaching a threshold.

Abstract: A microprocessor (62) for coupling to an external read/write memory (70) having an addressable storage space for storing data. The microprocessor includes a data storage circuit (76) for storing a portion of the data, where that portion of data comprises non-cacheable data. The microprocessor further includes a class storage circuit (80) for storing a class identifier corresponding to the portion of the non-cacheable data, as well as an input (TERMINATE) for receiving a terminate signal and an input (CLASS) for receiving a class signal. Lastly, the microprocessor includes an indicator (82) for indicating that the portion of the non-cacheable data in the data storage circuit is expired in response to assertions of the terminate signal and the class signal matching the class identifier.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A host module (2) including a host CPU (10) and a configurable expansion bus controller (28, 28', 128) is disclosed. The expansion bus controller (28, 28', 128) is configurable by way of configuration signals (BCFG) to be operable in various bus configurations for communicating signals between a module bus (IBUS) and external buses (XPCI1, XPCI0). These modes include combining the external buses (XPCI1, XPCI0) into a single bus of the 64-bit PCI type, operating the external buses (XPCI1, XPCI0) as separate 32-bit PCI buses, as separate CardBus buses, as separate AGP buses (either at one or multiple data transfers per cycle), or as combinations thereof. Certain of the configuration signals (BCFG) are used to select the clock frequencies at which the external buses (XPCI1, XPCI0) operate, in either of the 64-bit or 32-bit PCI protocols, or in the AGP bus protocol when present.

Abstract: A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected.

Abstract: A digital computing system (30). The digital computing system includes a memory (36) and a memory controller (34). The memory comprises at least one memory bank (B0), and that bank comprises a plurality of rows (R.sub.0 -R.sub.N) and a plurality of columns (C.sub.0 -C.sub.N). The memory controller circuit is coupled to control the memory, and comprises a first bus (38) for providing an address to the memory, and three additional buses (38, 40). A first of these additional buses provides a row address strobe signal (RAS*) to the memory, where assertion of the row address strobe signal represents an indication that an address on the bus is a valid row address directed to one of the plurality of rows. A second of these additional buses provides a column address strobe signal (CAS*) to the memory, where assertion of the column address strobe signal represents an indication that an address on the bus is a valid column address directed to at least one of the plurality of columns.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.