Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A computer includes a processor for processing data, and memory modules for storing the data. Each memory module includes a read-write memory and a configuration memory. The configuration memory (i) contains memory module characteristic information, (ii) is adapted for storing a sequence of binary data values, accessing the stored binary data only in sequential order, and only at the first data value or the next data value, and (iii) has a NEXT signal pin. The configuration memory is adapted for receiving at the NEXT signal pin, and responding to, a CAS signal used by standard DRAMs. In other features of the invention, the memory module characteristic information includes an identification code for the manufacturer of the memory module, a part number for the memory module, the depth of the memory, access times to read full and page, and delay times to read and write full and page.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: The abbreviated jump field of the present invention enables each instruction word within the data processing apparatus to cause an instruction sequence branch to one of a limited number of destinations. Each instruction word of the data processing apparatus includes a limited number of bits which are decoded to specify one of a small set of instruction destinations. One of the possible destinations is the normal default destination of the next instruction word. In addition a relatively large number of branch instructions have been found to specify a rather limited number of destinations. In the preferred embodiment of the present invention the limited number of bits of the abbreviated jump field is employed to specify one of these widely used destinations. The widely used destinations may include a return instruction, a conditional skip of execution of the next instruction and various error handling and error recovery routines.

Abstract: A computer system uses security labels for evey word in memory. Each access to a memory location requires that the security level of the memory location be compared to that of a process which is making the access. If the security level of the process does not dominate that of the memory location, access is denied. Each time a memory location is modified, it is assigned a security level consistent with the levels of all of the data which was used to modify the memory location.