Abstract: A flossing apparatus includes a handle assembly and a filament. The handle assembly includes first and second composite cores and first and second arms. The first composite core has at least one paper layer and at least one biodegradable plastic layer, and the second composite core has at least one paper layer and at least one biodegradable plastic layer. The filament is mounted to the first and second arms and captured between the first composite core and the second composite core.

Abstract: A video monitoring system can include multiple collectors to receive video beacon data from multiple video monitoring interface modules. At least one beacon stream is connected to receive data from multiple collectors. A processing module receives the beacon stream and provides a real-time event stream used for real-time data analysis and a video view stream used for long-term data analysis.

Abstract: A flossing apparatus includes a handle assembly and a filament. The handle assembly includes first and second composite cores and first and second arms. The first composite core has at least one paper layer and at least one biodegradable plastic layer, and the second composite core has at least one paper layer and at least one biodegradable plastic layer. The filament is mounted to the first and second arms and captured between the first composite core and the second composite core.

Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: Techniques for handling uncorrectable errors occurring during memory accesses reduce the likelihood of mis-correction of errors due to the presence of noise. When an uncorrectable memory error is detected in response to an access to a memory device, a memory controller managing the interface to the memory halts issuing of access requests to the memory device until a predetermined time period has elapsed. In-flight memory requests are marked for retry, and responses to pending request are flushed. A calibration command may be issued after the predetermined time period has elapsed. After the predetermined time period has elapsed and any calibration performed, the requests marked for retry are issued to the memory device.

Abstract: Techniques for handling uncorrectable errors occurring during memory accesses reduce the likelihood of mis-correction of errors due to the presence of noise. When an uncorrectable memory error is detected in response to an access to a memory device, a memory controller managing the interface to the memory halts issuing of access requests to the memory device until a predetermined time period has elapsed. In-flight memory requests are marked for retry, and responses to pending request are flushed. A calibration command may be issued after the predetermined time period has elapsed. After the predetermined time period has elapsed and any calibration performed, the requests marked for retry are issued to the memory device.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: Techniques for handling uncorrectable errors occurring during memory accesses reduce the likelihood of mis-correction of errors due to the presence of noise. When an uncorrectable memory error is detected in response to an access to a memory device, a memory controller managing the interface to the memory halts issuing of access requests to the memory device until a predetermined time period has elapsed. In-flight memory requests are marked for retry, and responses to pending request are flushed. A calibration command may be issued after the predetermined time period has elapsed. After the predetermined time period has elapsed and any calibration performed, the requests marked for retry are issued to the memory device.

Abstract: Techniques for handling uncorrectable errors occurring during memory accesses reduce the likelihood of mis-correction of errors due to the presence of noise. When an uncorrectable memory error is detected in response to an access to a memory device, a memory controller managing the interface to the memory halts issuing of access requests to the memory device until a predetermined time period has elapsed. In-flight memory requests are marked for retry, and responses to pending request are flushed. A calibration command may be issued after the predetermined time period has elapsed. After the predetermined time period has elapsed and any calibration performed, the requests marked for retry are issued to the memory device.

Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

Abstract: A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly.

Abstract: A method for performing refresh operations on a rank of memory devices is disclosed. After the completion of a memory operation, a determination is made whether or not a refresh backlog count value is less than a predetermined value and the rank of memory devices is being powered down. If the refresh backlog count value is less than the predetermined value and the rank of memory devices is being powered down, an Idle Count threshold value is set to a maximum value such that a refresh operation will be performed after a maximum delay time. If the refresh backlog count value is not less than the predetermined value or the rank of memory devices is not in a powered down state, the Idle Count threshold value is set based on the slope of an Idle Delay Function such that a refresh operation will be performed accordingly.

Abstract: Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.

Abstract: A bulk foodstuff dispenser for dispensing predetermined amounts of foodstuff from a hopper. An auger is driven by a handle capable of movement in two directions, while a clutch allows movement of the auger in only one direction. The forward movement of the handle causes the auger to rotate and move foodstuff forward to be dispensed. The forward movement of the handle is predetermined by setting a stopper, thereby regulating the amount of rotation of the auger and thus determining the portion of foodstuff to be dispensed. A spring returns the handle to its at rest position, so that the dispensing process may be repeated from the same handle position. Gears between the handle and the auger allow the handle to be pulled in a more ergonomically sound way.

Abstract: An oil lamp and fragrance release apparatus for providing a unique flame formation usable in a variety of decorative applications. The lamp includes a body that has an open upper end and that defines a chamber for carrying a combustible liquid. The lamp further includes a sheet wick having a lower end located in the chamber of the body, for contacting the combustible liquid, and an upper end projecting upwardly from the open upper end. The wick of inorganic material may be positioned between first and second plates arranged in a spaced, confronting relationship to enhance capillary action, may be freestanding stone of fibrous, permeable material or may be wrapped about a rigid plate. The wick provides a unique horizontal flame formation, while displaying décor on the outer surface of the flat wall. Optionally, the lamp may include scented oil and a conductive element to promote the release of fragrance upon heating, and the wick can be configured of material having high heat fragrance emanation.

Abstract: A bulk foodstuff dispenser for dispensing predetermined amounts of foodstuff from a hopper. An auger is driven by a handle capable of movement in two directions, while a clutch allows movement of the auger in only one direction. The forward movement of the handle causes the auger to rotate and move foodstuff forward to be dispensed. The forward movement of the handle is predetermined by setting a stopper, thereby regulating the amount of rotation of the auger and thus determining the portion of foodstuff to be dispensed. A spring returns the handle to its at rest position, so that the dispensing process may be repeated from the same handle position. Gears between the handle and the auger allow the handle to be pulled in a more ergonomically sound way.

Abstract: An apparatus for performing bus tracing with scalable bandwidth in a distributed memory symmetric multiprocesssor system is disclosed. The distributed memory symmetric multiprocessor system includes multiple processing units, each coupled to a memory module. Each of the processing units includes a memory controller and a bus trace macro (BTM) module. The memory controller is coupled to an interconnect for the symmetric multiprocessor system, and the BTM module is connected between the interconnect and the memory controller via two multiplexors. A subset of the BTM modules within the symmetric multiprocessor system is enabled for performing tracing operations such that address transactions on the interconnect are divided among the subset of the BTM modules to be selectively and separately intercepted by each BTM module within the subset of the BTM modules.

Abstract: A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

Abstract: Grip actuated control system to provide operational control of vehicle functions at a gripping surface of handlebar equipped vehicles. The system can be provided as original equipment and as an aftermarket addition or replacement for existent vehicle controls. The system includes one or more grip controls positioned adjacent a user's fingertips in a grip or glove assembly which are in communication with a control module. The control module is connected to existent or provided vehicle wiring and thus to respective operational equipment such that user actuation of a grip control induces the control module to provide a corresponding output to activate/deactivate or regulate the operation of the respective vehicle equipment. Communication between the grip controls and control module can be wireless for increased flexibility in installation and placement of the module on the vehicle. Combinations, sequences, and relative timing of the grip controls can provide numerous distinct control functions.