Patents by Inventor Steven Dodson

Steven Dodson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6601144
    Abstract: In addition to an address tag, a coherency state and an LRU position, each cache directory entry includes historical processor access and snoop operation information for the corresponding cache line. The historical processor access and snoop operation information includes different subentries for each different processor which has accessed the corresponding cache line, with subentries being “pushed” along the stack when a new processor accesses the subject cache line. Each subentries contains the processor identifier for the corresponding-processor which accessed the cache line, a processor access history segment, and a snoop operation history segment. The processor access history segment contains one or more opcodes identifying the operations which were performed by the processor, and timestamps associated with each opcode.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, John Steven Dodson, James Stephen Fields, Jr., Guy Lynn Guthrie
  • Patent number: 6587925
    Abstract: A method and system for processing a split data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device onto an address bus that is shared by a plurality of data storage devices within the hierarchical data storage system, wherein the data access request includes a target address and a source path tag. The source path tag includes at least one device identification tag that uniquely identifies at least one data storage device within each level of the hierarchical data storage system traversed by the data access request. In response to a data access request hit at a given data storage device, a data access response is delivered onto a data bus, wherein the data access response includes the source path tag and the target address.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6587924
    Abstract: A method and system for scarfing data during a data access transaction within a hierarchical data storage system. A data access request is delivered from a source device to a plurality of data storage devices. The access request includes a target address and a source path tag, wherein the source path tag includes a device identification tag that uniquely identifies a data storage device within a given level of the system traversed by the access request. A device identification tag that uniquely identifies the third party transactor within a given memory level is appended to the source path tag such that the third party transactor can scarf returning data without reserving a scarf queue entry.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6587926
    Abstract: A method and system for managing a data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device to multiple data storage devices within the hierarchical data storage system. The data access request includes a source path tag and a target address. At least one device identification tag is added to the source path tag, wherein the at least one device identification tag uniquely identifies a data storage device within each level of the hierarchical data storage system traversed by the data access request such that the data access transaction can be processed in accordance with source path information that is incrementally encoded within the data access request as the data access request traverses the hierarchical data storage system.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6581139
    Abstract: A set-associative cache memory having asymmetric latency among sets is disclosed. The cache memory has multiple congruence classes of cache lines. Each congruence class includes a number of sets organized in a set-associative manner. The cache memory further includes a means for accessing at least one of the sets faster than the remaining sets having an identical access latency.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: June 17, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, John Steven Dodson, James Stephen Fields, Jr., Guy Lynn Guthrie
  • Patent number: 6574714
    Abstract: A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: June 3, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Guy Lynn Guthrie
  • Patent number: 6571322
    Abstract: A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: May 27, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Guy Lynn Guthrie
  • Patent number: 6553442
    Abstract: In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits a token required to complete the global operation and identifies the global operation to be processed with the token, if granted. Upon receiving a combined response acknowledging both the token and operation portions of the combined request, the bus master treats the global operation as complete. If a combined response acknowledging the token portion of the combined request but retrying the operation portion (i.e., at least one snooper is busy processing a previous global operation), the bus master issues an operation request (only) for the operation portion of the combined request.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: April 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis
  • Patent number: 6553462
    Abstract: A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: April 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Guy Lynn Guthrie
  • Patent number: 6549989
    Abstract: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an additional cache state which specifically indicates that a processor has released its lock on a cache line after it has performed any necessary modifications.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: April 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, John Steven Dodson, Guy Lynn Guthrie, William John Starke
  • Patent number: 6532521
    Abstract: A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie, James Stephen Fields, Jr.
  • Patent number: 6516368
    Abstract: In response to a need to initiate one or more global operations, a bus master within a multiprocessor system issues a combined token and operation request in a single bus transaction on a bus coupled to the bus master. The combined token and operation request solicits a single existing token required to complete the global operations within the multiprocessor system and identifies the first of the global operations to be processed with the token, if granted. Once a bus master is granted the token, no other bus master will be granted the token until the current token owner explicitly requests release. The current token owner repeats the combined token and operation request for each global operation which needs to be initiated and, on the last global operation, issues a combined request with an explicit release. Acknowledgement of the combined request with release implies release of the token for use by other bus masters.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: February 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis
  • Patent number: 6510494
    Abstract: A method of operating a processing unit of a computer system, by issuing an instruction having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the pref etch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: January 21, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie, James Stephen Fields, Jr.
  • Publication number: 20030014593
    Abstract: A method and system for managing a data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device to multiple data storage devices within the hierarchical data storage system. The data access request includes a source path tag and a target address. At least one device identification tag is added to the source path tag, wherein the at least one device identification tag uniquely identifies a data storage device within each level of the hierarchical data storage system traversed by the data access request such that the data access transaction can be processed in accordance with source path information that is incrementally encoded within the data access request as the data access request traverses the hierarchical data storage system.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 16, 2003
    Applicant: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Publication number: 20030014591
    Abstract: A method and system for scarfing data during a data access transaction within a hierarchical data storage system. A data access request is delivered from a source device to a plurality of data storage devices. The access request includes a target address and a source path tag, wherein the source path tag includes a device identification tag that uniquely identifies a data storage device within a given level of the system traversed by the access request. A device identification tag that uniquely identifies the third party transactor within a given memory level is appended to the source path tag such that the third party transactor can scarf returning data without reserving a scarf queue entry.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 16, 2003
    Applicant: International Business Machines Corp.
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Publication number: 20030014592
    Abstract: A method and system for processing a split data access transaction within a hierarchical data storage system. In accordance with the method of the present invention, a data access request is delivered from a source device onto an address bus that is shared by a plurality of data storage devices within the hierarchical data storage system, wherein the data access request includes a target address and a source path tag. The source path tag includes at least one device identification tag that uniquely identifies at least one data storage device within each level of the hierarchical data storage system traversed by the data access request. In response to a data access request hit at a given data storage device, a data access response is delivered onto a data bus, wherein the data access response includes the source path tag and the target address.
    Type: Application
    Filed: July 12, 2001
    Publication date: January 16, 2003
    Applicant: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis
  • Patent number: 6507880
    Abstract: In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the global operation and identifies the global operation to be processed with the token, if granted. Bus snoopers contain a number of snooper queues for global operations equal to the number of global operation tokens employed within the multiprocessor system. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. Before completing the operation, the snooper watches for a combined response with a token number acknowledging either the combined request or a subsequent token request from the same processor, which indicates that the originating bus master has been granted a token for completing a global operation.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: January 14, 2003
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, Jody B. Joyner, Jerry Don Lewis
  • Publication number: 20030009643
    Abstract: A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node having a home system memory. The remote node includes a local interconnect, a processing unit and at least one cache coupled to the local interconnect, and a node controller coupled between the local interconnect and the node interconnect. The processing unit first issues, on the local interconnect, a read-type request targeting data resident in the home system memory with a flag in the read-type request set to a first state to indicate only local servicing of the read-type request. In response to inability to service the read-type request locally in the remote node, the processing unit reissues the read-type request with the flag set to a second state to instruct the node controller to transmit the read-type request to the home node.
    Type: Application
    Filed: June 21, 2001
    Publication date: January 9, 2003
    Applicant: International Business Machines Corp.
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields
  • Publication number: 20030009639
    Abstract: A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node including a home system memory. The remote node includes a plurality of snoopers coupled to a local interconnect. The plurality of snoopers includes a cache that caches a cache line corresponding to but modified with respect to data resident in the home system memory. The cache has a cache controller that issues a deallocate operation on the local interconnect in response to deallocating the modified cache line. The remote node further includes a node controller, coupled between the local interconnect and the node interconnect, that transmits the deallocate operation to the home node with an indication of whether or not a copy of the cache line remains in the remote node following the deallocation. In this manner, the local memory directory associated with the home system memory can be updated to precisely reflect which nodes hold a copy of the cache line.
    Type: Application
    Filed: June 21, 2001
    Publication date: January 9, 2003
    Applicant: International Business Machines Corp.
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields
  • Publication number: 20030009640
    Abstract: A non-uniform memory access (NUMA) data processing system includes a plurality of nodes coupled to a node interconnect. The plurality of nodes contain a plurality of processing units and at least one system memory having a table (e.g., a page table) resident therein. The table includes at least one entry for translating a group of non-physical addresses to physical addresses that individually specifies control information pertaining to the group of non-physical addresses for each of the plurality of nodes. The control information may include one or more data storage control fields, which may include a plurality of write through indicators that are each associated with a respective one of the plurality of nodes. When a write through indicator is set, processing units in the associated node write modified data back to system memory in a home node rather than caching the data.
    Type: Application
    Filed: June 21, 2001
    Publication date: January 9, 2003
    Applicant: International Business Machines Corp.
    Inventors: Ravi Kumar Arimilli, John Steven Dodson, James Stephen Fields