Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information).

Abstract: A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions and treats instructions in a different manner when they are loaded speculatively. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. The load requests are sent to the lower level cache when the upper level cache does not contain the value required by the load.

Abstract: A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line.

Abstract: Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are speculatively executed before the barrier operation completes on the system bus. The processor comprises a load/store unit (LSU) with a barrier operation (BOP) controller that permits load instructions subsequent to syncs in an instruction sequence to be speculatively issued by the LRQ prior to the return of the sync acknowledgment. Load data returned by the speculative load request is immediately forwarded to the processor's execution units for speculative execution with subsequent instructions. The returned data and results of subsequent operations are held temporarily in the rename registers. A multiprocessor speculation flag is set in the corresponding rename registers to indicate that the value is “barrier” speculative.

Abstract: A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line.

Abstract: A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line.

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of processors that are each associated with a respective one of a plurality of caches. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the data item. A coherency indicator in the first cache is set to a first state that indicates that the data item is valid. In response to another of the caches indicating an intent to store to the address indicated by the address tag while the coherency indicator is set to the first state, the coherency indicator in the first cache is updated to a second state that indicates that the address tag is valid and that the first data item in the first cache is invalid.

Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information).

Abstract: A cache memory having a programmable cache replacement scheme is disclosed. After a cache “miss,” a linefill operation is first preformed on a cache line. Subsequent to the linefill operation, the cache line is then assigned to an access status other than the most recently used status. The assignment of the access status is based on a programmable setting that defines an access status after a linefill operation and all other subsequent accesses.

Abstract: A method for ordering the time of issuing of a load instruction from a lower level (L2) cache controller to its L2 cache in a data processing system to enable delivery of a load data at a time it is required by its downstream dependency is disclosed. The method comprises the steps of (i) determining a cycle of dependency (CoD) of the load data, where the CoD corresponds to an exact synchronized timer (ST) time, measured in cycles, on which said data is required by said downstream dependency from the L2 cache, and (ii) issuing the load instruction to said L2 cache at said time to synchronize a providing of said data to a pipeline of a system resource with a request by its downstream dependency. In the preferred embodiment of the invention, a distance of dependency (DoD) value is first appended to the load instruction. The DoD value is then converted to a CoD value when a miss occurs at the internal (L1) cache.

Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information).

Abstract: A system which permits dynamic verification of the availability of a desired time at which to load a data requested by a load instruction. The system comprises (i) means for appending a time dependency value to the load instruction, where the time dependency value corresponds to the desired time, (ii) means for verifying that said desired time is available for loading said data, and (iii) means for sending an acknowledgement (ACK) when the desired time is available, where a processor reserves the system resources for accepting the data at the desired time in response to the ACK.

Abstract: A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).

Abstract: A system for time-ordered execution of load instructions. More specifically, the system enables just-in-time delivery of data requested by a load instruction. The system consists of a processor, an L1 data cache with corresponding L1 cache controller, and an instruction processor. The instruction processor manipulates a plurality of architected time dependency fields of a load instruction to create a plurality of dependency fields. The dependency fields holds a relative dependency value which is utilized to order the load instruction in a Relative Time-Ordered Queue (RTOQ) of the L1 cache controller. The load instruction is sent from RTOQ to the L1 data cache at a particular time so that the data requested is loaded from the L1 data cache at the time specified by one of the dependency fields. The dependency fields are prioritized so that the cycle corresponding to the highest priority field which is available is utilized.

Abstract: A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system.

Abstract: A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information).

Abstract: A method of maintaining cache-coherency in a multi-processor computer system provides new states to indicate that a sector in an upstream cache has been modified, without executing unnecessary bus transactions for the lower-level cache(s). These new “U” states can indicate which sector in the cache line was modified, or if the cache line was the subject of a cachable write-through operation. The protocol is implemented as an improvement to the prior-art “MESI” cache-coherency protocol. The new protocol is especially useful in handling allocate-and-zero instructions wherein data is modified in the cache (zeroed out) without first fetching the old data from memory. In the embodiment wherein there are only two sectors in a given cache line, three new states are provided to indicate which sector was modified, or whether any cachable write-through operation was performed on the cache line of the first-level cache.

Abstract: A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

Abstract: A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster).

Abstract: Upon snooping a combined data access and castout/deallocate operation initiating by a horizontal storage device, snoop logic determines, from coherency state information appended to either the combined operation or the combined response to the operation, whether the coherency state of the victim may be upgraded within the subject storage device. If so, the coherency state is upgraded to improve global data storage management. For instance, a cache line may be upgraded from the shared coherency state to the exclusive coherency state to improve data storage management under a given replacement policy.