Abstract: A monobit analog-digital converter (ADC) system and method are disclosed, the system comprising a front-end signal conditioning system equipped with a programmable attenuator and amplifier for processing analog signals, where the attenuator, which may include a cascade of programmable attenuator cells, is controlled by an attenuation control signal to adjust signal attenuation to cause a signal-to-noise ratio (SNR) in the negative domain, after which an amplifier amplifies the attenuated signal with the suitable SNR, where the amplified signal is then converted to a monobit signal by a monobit ADC, thereby achieving an ADC system that enables conditioning and digitizing of RF signals over a wide range of input signal powers with control over the output spectrum signal power and harmonics to achieve low-power real-time general-purpose broadband blocker detection for adaptive radios and for interference detection, main beam radar signal detection, and instantaneous frequency measurement, among other fields requ

Abstract: In one example, an RF oscillator system includes a laser source configured to emit laser light, a housing, a crystalline microresonator disposed within the housing, and a photonic integrated circuit disposed within the housing, the photonic integrated circuit including an optical waveguide network and configured to generate a clock signal based on the laser light. The RF oscillator system may further include at least one photonic wirebond configured to couple the laser light between the optical waveguide network and the crystalline microresonator via evanescent coupling; laser control circuitry disposed within the housing and configured to lock a frequency of the laser light to a resonance of the microresonator to generate the clock signal; and a direct digital synthesizer disposed within the housing and configured to produce a tunable oscillator signal based on the clock signal.

Abstract: A direct digital synthesis (DDS) device includes a first digital to analog converter (DAC) and a second DAC, wherein the first and second DACs are configured to respectively process first and second samples of a digital amplitude signal. The DDS device also includes a switch configured to receive first and second DAC output signals from the first and second DACs, respectively, and selectively switch among at least the first DAC output signal and the second DAC output signal to generate a combined signal. The DDS device also includes a signal mixer configured to receive the combined signal and a mixer clock signal, wherein the signal mixer is a multi-mode mixer further configured to operate in (i) a pass-through mode where the combined signal is provided as a mixed signal, and (ii) a mixing mode where the combined signal is mixed with the mixer clock signal, to generate the mixed signal.

Abstract: A direct digital synthesis (DDS) device includes a first digital to analog converter (DAC) and a second DAC, wherein the first and second DACs are configured to respectively process first and second samples of a digital amplitude signal. The DDS device also includes a switch configured to receive first and second DAC output signals from the first and second DACs, respectively, and selectively switch among at least the first DAC output signal and the second DAC output signal to generate a combined signal. The DDS device also includes a signal mixer configured to receive the combined signal and a mixer clock signal, wherein the signal mixer is a multi-mode mixer further configured to operate in (i) a pass-through mode where the combined signal is provided as a mixed signal, and (ii) a mixing mode where the combined signal is mixed with the mixer clock signal, to generate the mixed signal.

Abstract: A monobit analog-digital converter (ADC) system and method are disclosed, the system comprising a front-end signal conditioning system equipped with a programmable attenuator and amplifier for processing analog signals, where the attenuator, which may include a cascade of programmable attenuator cells, is controlled by an attenuation control signal to adjust signal attenuation to cause a signal-to-noise ratio (SNR) in the negative domain, after which an amplifier amplifies the attenuated signal with the suitable SNR, where the amplified signal is then converted to a monobit signal by a monobit ADC, thereby achieving an ADC system that enables conditioning and digitizing of RF signals over a wide range of input signal powers with control over the output spectrum signal power and harmonics to achieve low-power real-time general-purpose broadband blocker detection for adaptive radios and for interference detection, main beam radar signal detection, and instantaneous frequency measurement, among other fields requ

Abstract: Laser control circuitry is described. In one example, a laser controller integrated circuit (IC) includes first and second input ports, a sideband direct digital synthesizer (DDS) coupled to the first input port and configured to produce a modulation signal and a reference signal based on an input signal received via the first input port, the modulation signal and the reference signal having a same frequency. The laser controller IC further includes a Pound-Drever-Hall frequency-locking control loop coupled to the second input port and to the sideband DDS, and configured to produce a corrected DC bias current signal based on the reference signal and a measurement signal received via the second input port, and a thermal management circuit configured to produce at least one thermal control signal.

Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.

Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.

Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.

Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.

Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.

Abstract: A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.

Abstract: A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.

Abstract: A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC circuit configured according to an embodiment includes a current source associated with each bit of a digital word that is to be converted. Each current source is coupled to a current switch that is controlled by the associated bit. The DAC also includes a cascode device coupled to each of the current switches through a feed line. The DAC further includes a summing junction configured to generate an analog output signal corresponding to the digital word based on a sum of currents provided by the current sources, through the current switches and the feed lines. The cascode devices provide impedance matching and isolation between the feed lines and the summing junction to reduce signal reflections between the current switches and the summing junction to improve conversion performance.