Patents by Inventor Steven E. Turner
Steven E. Turner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11811415Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.Type: GrantFiled: June 18, 2021Date of Patent: November 7, 2023Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Shailendra Srinivas, Joseph D. Cali, Steven E. Turner
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Patent number: 11652488Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.Type: GrantFiled: March 8, 2022Date of Patent: May 16, 2023Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Steven E. Turner, Joseph D. Cali
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Publication number: 20220407524Abstract: A direct digital synthesizer (DDS) circuit. The circuit includes a first input to receive a first fixed frequency clock signal having a first frequency, a second input to receive a second fixed frequency clock signal having a second frequency lower than the first frequency, and an output to provide an output frequency that is based at least in part on a frequency control word (FCW). The DDS circuit may include a frequency correction circuit having a first input to receive the first clock signal, a second input to receive the second clock signal, and a third input to receive the FCW, and an output to provide a frequency error of the first clock signal, the frequency error determined using the second clock signal and FCW. Alternatively, or in addition to, the DDS circuit may include an all-digital phase lock loop to correct for frequency wander of the first clock signal.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Applicant: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Shailendra Srinivas, Joseph D. Cali, Steven E. Turner
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Publication number: 20220278687Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.Type: ApplicationFiled: March 8, 2022Publication date: September 1, 2022Inventors: Steven E. Turner, Joseph D. Cali
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Publication number: 20220245288Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Applicant: Tobii ABInventors: William R. Anderson, Steven E. Turner, Steven Pujia
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Patent number: 11303287Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.Type: GrantFiled: March 1, 2021Date of Patent: April 12, 2022Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Steven E. Turner, Joseph D. Cali
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Publication number: 20210073421Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.Type: ApplicationFiled: August 28, 2020Publication date: March 11, 2021Applicant: Tobii ABInventors: William R. Anderson, Steven E. Turner, Steven Pujia
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Patent number: 10698441Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.Type: GrantFiled: May 21, 2018Date of Patent: June 30, 2020Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Joseph D. Cali, Steven E. Turner
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Publication number: 20190384941Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.Type: ApplicationFiled: March 19, 2019Publication date: December 19, 2019Applicant: Tobii ABInventors: William R. Anderson, Steven E. Turner, Steven Pujia
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Publication number: 20190354134Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.Type: ApplicationFiled: May 21, 2018Publication date: November 21, 2019Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.Inventors: Joseph D. Cali, Steven E. Turner
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Patent number: 10282563Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.Type: GrantFiled: February 5, 2010Date of Patent: May 7, 2019Assignee: Tobii ABInventors: William Robert Anderson, Steven E. Turner, Steven Pujia
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Patent number: 10193646Abstract: A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.Type: GrantFiled: May 30, 2017Date of Patent: January 29, 2019Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Steven E. Turner
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Publication number: 20180351677Abstract: A true single-phase clocked multiplexer for outputting one of a plurality of input signals in synchronization with a clock signal and as selected by at least one select signal is provided. The multiplexer includes first transistors, second transistors, a first node between the first transistors, a second node between the second transistors, a third node coupled to the first node by one of the first transistors and to the second node by one of the second transistors, and a pre-charge transistor to couple the third node to a first voltage level. The first transistors are coupled to the first voltage level and configured to turn on in response to a gate voltage of a second voltage level different from the first voltage level. The second transistors are coupled to the second voltage level and configured to turn on in response to a gate voltage of the first voltage level.Type: ApplicationFiled: May 30, 2017Publication date: December 6, 2018Applicant: BAE Systems Information and Electronic Systems Integration IncInventor: Steven E. Turner
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Patent number: 10097199Abstract: A digital to analog converter (DAC) circuit is disclosed which employs isolation providing cascode devices to reduce data dependent signal distortion. A DAC circuit configured according to an embodiment includes a current source associated with each bit of a digital word that is to be converted. Each current source is coupled to a current switch that is controlled by the associated bit. The DAC also includes a cascode device coupled to each of the current switches through a feed line. The DAC further includes a summing junction configured to generate an analog output signal corresponding to the digital word based on a sum of currents provided by the current sources, through the current switches and the feed lines. The cascode devices provide impedance matching and isolation between the feed lines and the summing junction to reduce signal reflections between the current switches and the summing junction to improve conversion performance.Type: GrantFiled: February 12, 2018Date of Patent: October 9, 2018Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Lawrence J. Kushner, Mark E. Stuenkel, Steven E. Turner
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Patent number: 9900012Abstract: Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.Type: GrantFiled: April 15, 2016Date of Patent: February 20, 2018Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Joseph D. Cali, Curtis M. Grens, Lawrence J. Kushner, Steven E. Turner
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Patent number: 9571078Abstract: According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock.Type: GrantFiled: July 24, 2015Date of Patent: February 14, 2017Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Steven E. Turner, Michael P. Anthony
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Patent number: 9536097Abstract: Methods and apparatus for displaying visual content on a display such that the content is comprehensible only to an authorized user for a visual display system such as a computer, a television, a video player, a public display system (including but not limited to a movie theater), a mobile phone, an automated teller machine (ATM), voting booths, kiosks, security screening workstations, tactical displays and other systems where information is displayed for viewing.Type: GrantFiled: May 1, 2013Date of Patent: January 3, 2017Inventors: William Anderson, Steven E. Turner, Steven J. Pujia, George L. Heron
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Patent number: 9479185Abstract: A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.Type: GrantFiled: December 14, 2015Date of Patent: October 25, 2016Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Joseph D. Cali, Steven E. Turner
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Publication number: 20160308536Abstract: Frequency divider techniques are disclosed which can be used to address two problems: when an incorrect division occurs if the modulus control changes before the divide cycle is complete, and when an incorrect division occurs due to a boundary crossing (e.g., power-of-2 boundary crossing in a fractional-N PLL application). In one embodiment, a frequency divider is provided comprising a plurality of flip-flops operatively coupled to carry out division of an input frequency, and configured to generate a modulus output and receive a divided clock signal of a previous cell. An additional flip-flop is selectively clocked off one of the modulus output or the divided clock of the previous stage, depending at least in part on a Skip control signal applied to a data input of the additional flip-flop, and is further configured to selectively reset the plurality of flip-flops to a state that will result in a correct divide ratio.Type: ApplicationFiled: April 15, 2016Publication date: October 20, 2016Applicant: BAE Systems Information and Electronic Systems Int egration Inc.Inventors: JOSEPH D. CALI, CURTIS M. GRENS, LAWRENCE J. KUSHNER, STEVEN E. TURNER
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Patent number: 9450595Abstract: Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit. The system may also include a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors. The system may further include a plurality of output ports, each output port coupled to one of the cascode transistors. The cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor. The cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.Type: GrantFiled: December 3, 2015Date of Patent: September 20, 2016Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Joseph D. Cali, Lawrence J. Kushner, Steven E. Turner