Abstract: A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase coherence of a synthesized frequency includes a phase coherent delta-sigma modulator (DSM) having a plurality of feed-forward accumulator stages. The DSM is operatively coupled to a reference clock configured to generate a cyclical reference signal. The DSM configured to count a number of cycles of the reference signal, to cause, at each cycle of the reference signal, each of the stages of the DSM to accumulate a sum of a previous stage of the DSM, and to multiply each sum by a fractional divide word to produce a multiplier output, thereby causing the DSM to output a sequence of signals that tracks with the reference clock.

Abstract: Techniques are provided for a switched output digital to analog converter employing an N-path cascode output switch. An example system may include a plurality of cascode transistors coupled in parallel to an output stage of a current mode digital to analog converter (DAC) circuit. The system may also include a plurality of control ports, each of the control ports coupled to a gate of one of the cascode transistors. The system may further include a plurality of output ports, each output port coupled to one of the cascode transistors. The cascode transistors are configured to switch the output stage of the DAC to the output port of the transistor in response to a routing control signal applied to the control port of the transistor. The cascode transistors are High Electron Mobility Transistors (HEMT) fabricated from Gallium Nitride.

Abstract: According to an embodiment, an improved flying adder circuit, comprises a fine clock, a coarse pulse clock, a rising edge triggered output connected to both the fine clock and the coarse pulse clock, a pulse clock connected to the rising edge triggered output, an adder, a 12-bit register situated to receive a signal from the adder and the pulse clock, and a single bit register situated to receive a signal from the pulse clock.

Abstract: In a fractional-n Phase Locked Loop the frequency control word multiplies by the output of a reference counter to provide the carry bit utilized in n/n+1 switching.

Abstract: Methods and apparatus for displaying visual content on a display such that the content is comprehensible only to an authorized user for a visual display system such as a computer, a television, a video player, a public display system (including but not limited to a movie theater), a mobile phone, an automated teller machine (ATM), voting booths, kiosks, security screening workstations, tactical displays and other systems where information is displayed for viewing.

Abstract: A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.

Abstract: In a fractional-n Phase Locked Loop the frequency control word multiplies by the output of a reference counter to provide the carry bit utilized in n/n+1 switching.

Abstract: Methods and apparatus for displaying visual content on a display such that the content is comprehensible only to an authorized user for a visual display system such as a computer, a television, a video player, a public display system (including but not limited to a movie theater), a mobile phone, an automated teller machine (ATM), voting booths, kiosks, security screening workstations, tactical displays and other systems where information is displayed for viewing.

Abstract: A phase accumulator generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase and thus phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency.

Abstract: A digital to analog converter (DAC) method and apparatus employs a multiplying-adding DAC, eliminating digital adder circuitry. Examples are given for multiplying a 3-bit binary number by a 2-bit binary number; however, there are no limitations to the bit-widths of the numbers to be multiplied. The multiplying-adding DAC method can be scaled up or down in bit-width by feeding the DAC with partial sums and adjusting the DAC weights accordingly. An analog to digital converter (ADC) can be placed after the DAC to generate a digital output. By multiplexing preset digital data into the DAC core for return to zero (RTZ), a true zero that is the midpoint of the DAC output range is achieved. It does not return to a rail for single-ended outputs. RTZ in DAC circuits doubles the null frequency of sin(x)/x roll-off inherent in DACs and also helps reduce switching glitches in the DAC output.

Abstract: A DDS system is disclosed that is configured to provide a variable clock delay that allows timing of data coming out of the ROM to be adjusted. In one example case, a DDS system is provided that includes a ROM for storing phase-to-amplitude conversion data and generating digital amplitude values corresponding to respective digital phase values, and delay circuitry for adjusting timing of data output by the ROM to compensate for propagation delay of the DDS system. The delay circuitry may include, for instance, delay elements that can be selected alone or in combination to adjust the timing. The timing can be adjusted, for example, by adjusting delay of a clock signal that clocks one or more ROM pipeline registers. The system may include a phase accumulator and DAC, and adjusting the timing may include adjusting delay of a clock signal that clocks one or more DAC pipeline registers.

Abstract: A phase accumulator generates phase data for a direct digital synthesis (DDS) device based on a reference phase to provide analog sinusoidal outputs that are locked to the reference phase and thus phase coherent. The frequency of a sinusoidal DDS output may be controlled by changing a frequency control word (FCW) provided to the phase accumulator without affecting the incrementing reference phase. The sinusoidal DDS output is based on a multiple of the FCW and the reference phase and thus remains locked to the reference phase, providing phase coherency even when the FCW changes to change the frequency.

Abstract: The present system provides a website for distributing a plurality of content data streams converted into a common format, wherein each content data stream is encrypted and transmission of the content data stream is a function of available transmission rates to a given remote device.

Abstract: Techniques are disclosed for improving the dynamic performance of digital-to-analog converters (DAC), by compensating for the unique delay characteristics of each bit in the DAC summing junction to equalize the delays. In one example case, a DAC device is provided that includes a plurality of current sources and a plurality of switches, each switch operatively coupled between a corresponding one of the current sources and a summing junction that is operatively coupled to an analog output. The device further includes a plurality of switch control lines configured to receive a digital input, each switch control line for controlling a corresponding one of the switches. The device further includes a plurality of compensation delay elements, each associated with a corresponding one of the switch control lines and providing a different delay value.

Abstract: A digital to analog converter (DAC) method and apparatus employs a multiplying-adding DAC, eliminating digital adder circuitry. Examples are given for multiplying a 3-bit binary number by a 2-bit binary number; however, there are no limitations to the bit-widths of the numbers to be multiplied. The multiplying-adding DAC method can be scaled up or down in bit-width by feeding the DAC with partial sums and adjusting the DAC weights accordingly. An analog to digital converter (ADC) can be placed after the DAC to generate a digital output. By multiplexing preset digital data into the DAC core for return to zero (RTZ), a true zero that is the midpoint of the DAC output range is achieved. It does not return to a rail for single-ended outputs. RTZ in DAC circuits doubles the null frequency of sin(x)/x roll-off inherent in DACs and also helps reduce switching glitches in the DAC output.

Abstract: Computer display privacy and security for computer systems. In one aspect, the invention provides a computer-controlled system for regulating the interaction between a computer and a user of the computer based on the environment of the computer and the user. For example, the computer-controlled system provided by the invention comprises an input-output device including an image sensor configured to collect facial recognition data proximate to the computer. The system also includes a user security parameter database encoding security parameters associated with the user; the database is also configured to communicate with the security processor. The security processor is configured to receive the facial recognition data and the security parameters associated with the user, and is further configured to at least partially control the operation of the data input device and the data output device in response to the facial recognition data and the security parameters associated with the user.

Abstract: A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.

Abstract: A passband echo canceller achieves improved performance by providing a signal having a substantially uniform power spectral density to an adaptive echo canceller; the improved input signal is substantially uniform from approximately zero hertz to one half the operating or sample frequency of the echo canceller. This signal may comprise that range of frequencies occupied by the transmitted spectrum with added out of band noise.