Abstract: A method for controlling a process of manufacturing semiconductor devices, the method including: obtaining a first control grid associated with a first lithographic apparatus used for a first patterning process for patterning a first substrate; obtaining a second control grid associated with a second lithographic apparatus used for a second patterning process for patterning a second substrate; based on the first control grid and second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data relating to metrology performed on the bonded substrate; and determining a correction for performance of the bonding step based on the bonded substrate metrology data, the determining a correction including determining a co-optimized correction for the bonding step and for the first patterning process and/or second patterning process.

Abstract: A method for controlling a process of manufacturing semiconductor devices, the method including: obtaining a first control grid associated with a first lithographic apparatus used for a first patterning process for patterning a first substrate; obtaining a second control grid associated with a second lithographic apparatus used for a second patterning process for patterning a second substrate; based on the first control grid and second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data relating to metrology performed on the bonded substrate; and determining a correction for performance of the bonding step based on the bonded substrate metrology data, the determining a correction including determining a co-optimized correction for the bonding step and for the first patterning process and/or second patterning process.

Abstract: A method for controlling a process of manufacturing semiconductor devices, the method including: obtaining a first control grid associated with a first lithographic apparatus used for a first patterning process for patterning a first substrate; obtaining a second control grid associated with a second lithographic apparatus used for a second patterning process for patterning a second substrate; based on the first control grid and second control grid, determining a common control grid definition for a bonding step for bonding the first substrate and second substrate to obtain a bonded substrate; obtaining bonded substrate metrology data including data relating to metrology performed on the bonded substrate; and determining a correction for performance of the bonding step based on the bonded substrate metrology data, the determining a correction including determining a co-optimized correction for the bonding step and for the first patterning process and/or second patterning process.

Abstract: Disclosed is a method of determining a characteristic of interest, in particular focus, relating to a structure on a substrate formed by a lithographic process, and an associated patterning device and lithographic system. The method comprises forming a modified substrate feature on the substrate using a corresponding modified reticle feature on a patterning device, the modified substrate feature being formed for a primary function other than metrology, more specifically for providing a support for a vertically integrated structure. The modified reticle feature is such that said modified substrate feature is formed with a geometry dependent on the characteristic of interest during formation. The modified substrate feature can be measured to determine said characteristic of interest.

Abstract: A solar cell panel with a bottom cover plate and an electrically conductive bus bar. A top cover plate having at least one electrically conductive land in communication with a bottom surface of the top cover plate. The land having a height extending from the bottom surface of the top cover plate. An array of rows and columns of solar cell chips lying between the bottom cover plate and the top cover plate. Each solar cell chip of the array having an anode adjacent to a top surface and a cathode adjacent to a bottom surface. The bus bar in electrical communication with each cathode of each solar cell chip of the array. Each land in electrical contact with each anode of a solar cell chip of the array. An opening formed between adjacent lands wherein the opening extends at least the height of the lands.

Abstract: Disclosed is a method of determining a characteristic of interest, in particular focus, relating to a structure on a substrate formed by a lithographic process, and an associated patterning device and lithographic system. The method comprises forming a modified substrate feature on the substrate using a corresponding modified reticle feature on a patterning device, the modified substrate feature being formed for a primary function other than metrology, more specifically for providing a support for a vertically integrated structure. The modified reticle feature is such that said modified substrate feature is formed with a geometry dependent on the characteristic of interest during formation. The modified substrate feature can be measured to determine said characteristic of interest.

Abstract: A solar cell panel with a bottom cover plate and an electrically conductive bus bar. A top cover plate having at least one electrically conductive land in communication with a bottom surface of the top cover plate. The land having a height extending from the bottom surface of the top cover plate. An array of rows and columns of solar cell chips lying between the bottom cover plate and the top cover plate. Each solar cell chip of the array having an anode adjacent to a top surface and a cathode adjacent to a bottom surface. The bus bar in electrical communication with each cathode of each solar cell chip of the array. Each land in electrical contact with each anode of a solar cell chip of the array. An opening formed between adjacent lands wherein the opening extends at least the height of the lands.

Abstract: A solar cell panel and method of forming a solar cell panel. The method includes a: forming an electrically conductive bus bar on a top surface of a bottom cover plate; forming an electrically conductive contact frame proximate to a bottom surface of a top cover plate, the top cover plate transparent to visible light; and placing an array of rows and columns of solar cell chips between the bottom cover plate and the top cover plate, each solar cell chip of the array of solar cell chips comprising an anode adjacent to a top surface and a cathode adjacent to a bottom surface of the solar cell chip, the bus bar electrically contacting each cathode of each solar cell chip of the array of solar cell chips and the contact frame contacting each anode of each solar cell chip of the array of solar cell chips.

Abstract: A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.

Abstract: A magnetic head in one embodiment includes a bottom pole; a top pole positioned above a plane extending through the bottom pole and parallel to a plane of deposition of the bottom pole, wherein the top pole is at least partially offset from the bottom pole in a direction parallel to a plane of deposition of the top pole; a first write gap in the top pole; and a first coil for generating a magnetic flux across the first write gap. A method in one embodiment includes forming a bottom pole; forming a top pole above a plane extending through the bottom pole and parallel to a plane of deposition of the bottom pole, wherein the top pole is at least partially offset from the bottom pole in a direction parallel to a plane of deposition of the top pole, wherein at least one write gap is formed in the top pole; forming side poles for coupling the top and bottom poles; and forming a first coil for generating a magnetic flux across the first write gap.

Abstract: An apparatus for plating a magnetic film on a substrate includes: a track including a plurality of stopping points along the track; a permanent magnet placed on the track such that the permanent magnet can be moved along the track towards and away from the stopping points; at least one plating tank positioned on the stopping point; and a removable high permeability iron flux concentrator inserted into gaps between the substrate and inside walls of the plating tank, substantially surrounding the substrate and extending around and under the substrate.

Abstract: A method of manufacturing a solar cell. The method includes the steps of providing a substrate, applying a first dopant to a first surface, applying a second dopant to a second surface, covering the doped first surface with a hard mask, applying a third dopant to the substrate side, removing the hard mask, applying a pattern of first electrical contacts to the doping pattern, and applying a pattern of second electrical contacts to the doped second surface, the pattern of second electrical contacts and the doping pattern being straight-lined opposed.

Abstract: An apparatus for plating a magnetic film on a substrate includes: a track including a plurality of stopping points along the track; a permanent magnet placed on the track such that the permanent magnet can be moved along the track towards and away from the stopping points; at least one plating tank positioned on the stopping point; and a removable high permeability iron flux concentrator inserted into gaps between the substrate and inside walls of the plating tank, substantially surrounding the substrate and extending around and under the substrate.

Abstract: An apparatus for plating a magnetic film on a substrate includes: a track including a plurality of stopping points along the track; a permanent magnet placed on the track such that the permanent magnet can be moved along the track towards and away from the stopping points; at least one plating tank positioned on the stopping point; and a removable high permeability iron flux concentrator inserted into gaps between the substrate and inside walls of the plating tank, substantially surrounding the substrate and extending around and under the substrate.

Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.

Abstract: A solar cell panel and method of forming a solar cell panel. The method includes a: forming an electrically conductive bus bar on a top surface of a bottom cover plate; forming an electrically conductive contact frame proximate to a bottom surface of a top cover plate, the top cover plate transparent to visible light; and placing an array of rows and columns of solar cell chips between the bottom cover plate and the top cover plate, each solar cell chip of the array of solar cell chips comprising an anode adjacent to a top surface and a cathode adjacent to a bottom surface of the solar cell chip, the bus bar electrically contacting each anode of each solar cell chip of the array of solar cell chips and the contact frame contacting each anode of each solar cell chip of the array of solar cell chips.

Abstract: A method of manufacturing a solar cell. The method includes the steps of providing a substrate, applying a first dopant to a first surface, applying a second dopant to a second surface, covering the doped first surface with a hard mask, applying a third dopant to the substrate side, removing the hard mask, applying a pattern of first electrical contacts to the doping pattern, and applying a pattern of second electrical contacts to the doped second surface, the pattern of second electrical contacts and the doping pattern being straight-lined opposed.

Abstract: A magnetic head in one embodiment includes a bottom pole; a top pole positioned above a plane extending through the bottom pole and parallel to a plane of deposition of the bottom pole, wherein the top pole is at least partially offset from the bottom pole in a direction parallel to a plane of deposition of the top pole; a first write gap in the top pole; and a first coil for generating a magnetic flux across the first write gap. A method in one embodiment includes forming a bottom pole; forming a top pole above a plane extending through the bottom pole and parallel to a plane of deposition of the bottom pole, wherein the top pole is at least partially offset from the bottom pole in a direction parallel to a plane of deposition of the top pole, wherein at least one write gap is formed in the top pole; forming side poles for coupling the top and bottom poles; and forming a first coil for generating a magnetic flux across the first write gap.

Abstract: A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.