METHOD OF FABRICATING SOLAR CELL CHIPS
A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.
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This application is a division of application Ser. No. 12/189,911, filed Aug. 12, 2008, now pending, which is hereby incorporated herein by reference.
FIELD OF THE INVENTIONThe present invention relates to the field of solar cells; more specifically, it relates to a method of fabricating a solar cell.
BACKGROUND OF THE INVENTIONSolar cells or solar concentrators are semiconductor devices capable of generating electricity using the photovoltaic effect. The relatively high cost of fabricating solar cells has seriously limited the widespread use of solar cells. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.
SUMMARY OF THE INVENTIONOne aspect of the present invention is a method, comprising: creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers.
The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
In
In
Alternatively, the process described in
The processes illustrate in
In a first method, masking layer 125 is a dielectric layer and openings 127 are formed photolithographically. A photolithographic process is one in which a photoresist layer is applied to a surface, the photoresist layer exposed to actinic radiation through a patterned photomask and the exposed photoresist layer developed to form a patterned photoresist layer. After etching openings 127, the photoresist layer is removed and an N-doped glass layer (e.g., phospho-silicate glass) applied (either spun on or sputtered on as described supra for layer 112 of
In a second method, masking layer 125 is itself a patterned photoresist layer and an N-type ion implantation (e.g., phosphorus or arsenic or both) into bottom surface 120 followed by an activation anneal (e.g., of about 800° C. or higher) to form emitters 130. The ion-implantation process is highly compatible with conventional integrated circuit chip fabrication. Masking layer 125 is then removed.
For exemplary purposes,
In
In
In
Alternatively, conventional subtractive etch or damascene wire processes may be used to form contact frame 170 and bus bar 175 in two separate operations. A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited on a top surface of the dielectric, and a CMP process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires. In the case of damascene processes, antireflective layer 145 and bottom passivation layer 140 act as polish stops.
In step 225 a solar cell process route is created. This route may include tools used only for conventional integrated circuit (IC) fabrication or a combination of tools used for IC fabrication and tools used only for solar cell (SC) fabrication. In step 230, a lot of solar cell wafers for solar cell manufacture is released to the manufacturing facility. In step 235 the solar cell lot is placed in a tool queue. Generally there is a queue for each tool or group of tools that can perform the process indicated by the route.
In step 240 an integrated circuit chip process route is created. In step 245, a lot of integrated circuit chip wafers for integrated circuit chip manufacture is released to the manufacturing facility. In step 250 the integrated circuit chip lot is placed in a tool queue. The solar cell lot queue of step 235 and the integrated circuit chip queue of step 250 may be the same queue.
From steps 235 and 250 the method proceeds to step 255 where it is determined if the tool for the particular queue has become available. If the tool is not available the method loops back to steps 235 or 250. If in step 255 a tool becomes available, then in step 260 it is determined if an integrated circuit chip lot is waiting for that tool. If there is an integrated circuit chip lot waiting to be processed through the tool, then in step 265, the integrated circuit chip lot is processed through the tool and in step 270 is determined if integrated chip fabrication for that lot is complete. If not, the method loops to step 250 where the integrated circuit chip lot is placed in the queue for the next processing tool on its route.
Returning to step 260, If there is no integrated circuit chip lot waiting, then in step 275, it is determined if a solar cell lot is waiting to be processed through tool. If so, then in step 280 the solar cell lot is processed through the tool and in step 285 is determined if solar cell fabrication for that lot is complete. If not, the method loops to step 235 where the solar cell lot is placed in the queue for the next processing tool on its route.
Returning to step 275, if there is no solar cell lot waiting then the method loops through connector A to step 255. One feature of the flowchart of
Thus the embodiments of the present invention have migrated the costs of fabricating solar cells by using combinations of conventional semiconductor processes, integrating solar cell fabrication into conventional integrated circuit chip fabrication facilities and utilizing scrap integrated circuit chip wafers.
The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Claims
1. A method, comprising:
- creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility;
- creating a solar cell process route for fabricating solar cells using solar cell wafers in said integrated circuit fabrication facility;
- releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of said an integrated circuit fabrication facility; and
- processing said solar cell wafers on at least some tools of said integrated circuit fabrication facility used to process said integrated circuit wafers.
2. The method of claim 1, further including:
- when both solar cell wafers and integrated circuit wafers are present in a same tool queue of a particular tool of said integrated circuit fabricating facility, processing said integrated circuit wafers on said particular tool before processing said solar cell wafers on said particular tool.
3. The method of claim 1, further including:
- when both solar cell wafers and integrated circuit wafers are present in a same tool queue of a particular tool of said integrated circuit fabricating facility, processing said integrated circuit wafers on said particular tool before processing said solar cell wafers on said particular tool except if a particular solar cell wafer has been in said particular tool queue for greater than a target time, then processing that particular solar cell wafer before any integrated circuit wafers in said tool queue of said particular tool.
4. The method of claim 1, further including;
- selecting scrap integrated circuit wafers from said integrated circuit fabrication facility; and
- recycling said scrap integrated circuit wafers to form said solar cell wafers.
5. The method of claim 4, wherein said recycling includes:
- etching said scrap integrated circuit wafers;
- after said etching, grinding said scrap integrated circuit wafers; and
- after said grinding, chemical-mechanical-polishing said scrap integrated circuit wafers.
6. The method of claim 1, further including:
- singulating said solar cell wafers into individual solar cell chips.
7. The method of claim 6, wherein said solar cell chips range in surface area from about 25 mm2 to about 400 mm2.
8. The method of claim 1, wherein said solar cell wafers are additionally processed on one or more tools used only for fabricating solar cell chips.
9. The method of claim 1, wherein after processing said solar cell wafers up to a singulating step, said solar cell wafers include solar cell chips having different surface areas.
10. The method of claim 1, further including performing the following process steps on said solar cell wafers:
- forming a P-doped layer and an N-doped layer in a solar cell wafer, said P-doped layer adjacent to a top surface of said solar cell wafer and said N-doped layer adjacent to a bottom surface of said solar cell wafer;
- forming a dielectric top passivation layer on said top surface of said solar cell wafer and a dielectric bottom passivation layer on said top surface of said solar cell wafer;
- forming an antireflective coating on said top passivation layer;
- photolithographically forming a first set of openings through said antireflective coating and through said top passivation layer to said P-doped layer and photolithographically forming a second set of openings through said bottom passivation layer to said N-doped layer;
- forming first metal silicide contacts to said P-doped layer and second metal silicide contacts to said N-doped layer in said first and second openings respectively; and
- forming metal contact frames on said first metal silicide contacts and metal bus bars on said second metal silicide contacts.
11. The method of claim 10:
- wherein said photolithographically forming said first set of openings includes defining first openings in a first hardmask layer and after forming said first set of opening, removing said hardmask layer; and
- wherein said photolithographically forming said second set of openings includes defining second openings in a second hardmask layer and after forming said second set of opening, removing said hardmask layer.
12. The method of claim 1, wherein said bus bar is a plate.
13. The method of claim 1, wherein said bus bar comprises a grid of intersecting orthogonal wires.
14. The method of claim 1, wherein said bus bar comprises a set of parallel wires.
Type: Application
Filed: Aug 3, 2010
Publication Date: Dec 2, 2010
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Hans-Juergen Eickelmann (Nieder-Hilbersheim), Michael Haag (Rodenbach), Harold J. Hovel (Katonah, NY), Rainer Klaus Krause (Main-Kostheim), Markus Schmidt (Seibersbach), Xiaoyan Shao (Yorktown Heights, NY), Steven Erik Steen (Peekskill, NY)
Application Number: 12/849,448
International Classification: H01L 31/18 (20060101); H01L 21/027 (20060101); H01L 21/283 (20060101);