Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.

Abstract: A milli-mode system has a processor state unit (R-unit) with register space into which those system operating registers and control latches, which make up the processor architected state, are mapped. This processor state unit, which includes a processor state register array and associated controls, receives all state updates from the processor as data and register addresses.

Abstract: A special inillicode instruction "Load With Access Test" explicitly detects access exceptions for storage operands while retaining control in the current millicode routine to insure exceptions are handled correctly and with the right priority. The millicode Load With Access Test instruction operates similarly to the ESA/390 Load instruction except that access exception code is set, interrupts are blocked and the serialization is forced to purge the instruction pipeline and reset the pipeline control without redirection of the instruction stream.

Abstract: A millicode method for packing the hexadecimal digits from a plurality of bytes in each of two millicode registers (R1,R1) into one of the two millicode registers extracts the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R1 and the rightmost hexadecimal digit from each of a plurality of bytes stored in millicode register R2 and stores hexadecimal digits from said extracting step in millicode register R1 with each hexadecimal digit extracted from a byte in register R1 and from a byte in register R2 stored in millicode register R1 in register R1 positions occupied by said plurality of bytes stored in register R1 prior to said extraction step.

Abstract: A special Program Status Word (PSW) millicode routine, tests the validity of the PSW with three simple millicode instructions. Testing for access exceptions is executed by a special millicode instruction "Load With Access Test", which explicitly detects access exceptions for storage operands while retaining control in the current millicode routine. A Translate and Test (TRT) routine uses a table of 256 bytes to translate a string of bytes. Each string is used as an index into the table, and the selected table byte is fetched. For Translate and Test, the selected bytes are tested, and the first non-zero table byte selected is returned to the program in a general register along with the address of the string byte which selected it; translate and test also sets the condition code, and does not update storage.

Abstract: In a milli-mode processor, bits (0-6) of an access list entry token (ALET) in the program access register must be zeros in order for access register translation to be successful. When the ALET is being copied from a program access register to a millicode access register, bits 0-3 of ALET, written into the millicode access register, are set to the access register number of the program access register from which the data is being read. This establishes the affinity between the program access register number and any logical fetches which might be attempted by millicode.

Abstract: A milli-mode routine handles a quiesce interrupt, and causes all the processors in the system to enter a quiesced state. A single bit of a millicode control register indicates a quiesced state and drives an output of the processor to indicate the processor is in a quiesced state. The processor receives a signal indicating all processors in the system are in a quiesced state and latches this value. The output of this latch is sent to the processor instruction unit for use as a millicode branch condition.

Abstract: A pipelined computer processor in a milli-mode architected state tests the validity of a program status word with a mask stored in a millicode general register. The mask indicates bits in the program status word which are to be zeros if the word is valid. A logical AND operation is performed between correspondingly positioned bits in the word and bits in the mask and in addition the status of at least one other bit in the word is checked, a bit other than a correspondingly positioned bit.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

Abstract: A millicode instruction loads a millicode address extension register with extended address bits, and an operand access control register that signals when a logical address is to be extended by the extra bits, and when it should be treated as only a 31 bit address.

Abstract: Retry trap in the processor system detects the occurrence of a hardware retry during a millicode routine. In operation, millicode resets the retry trap to "O" at the start of a millicode sequence that is sensitive to a retry operation being at some stage of the millicode sequence. The millicode routine tests the retry latch state at one or more points in the sequence to determine if a retry has occurred since the start of the sequence, which is sensitive to a retry operation. The action taken in response to a determination that a retry operation has occurred depends upon the type of potential damage to the system state as a result of the occurrence of the retry operation during the millicode sequence.

Abstract: In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.