Abstract: One embodiment of the invention is an integrated circuit having: (i) an array of flash transistors formed on a substrate and arranged in one or more rows, each flash transistor having a control gate, wherein, in each row, the control gates are connected to a word line; and (ii) for each word line, at least one diode structure formed on the substrate and having first and second diodes, each diode having a cathode and an anode, wherein the word line is connected to the cathode of the first diode and to the anode of the second diode.

Abstract: A process of fabricating a semiconductor device includes forming a device region including a non-volatile memory element and forming a utility layer overlying the device region, where the utility layer is a dielectric material formed by RTCVD. The utility layer preferably has a hydrogen content below that necessary to reduce the data retention of the non-volatile memory element in the device region. The utility layer can function as one or more of an etch-stop layer, a diffusion barrier layer, or an insulating layer.

Abstract: A non-volatile memory cell at least partially formed in a semiconductor substrate, comprising a first avalanche injection element having a first active region of a first conductivity type and a second active region of a second conductivity type, separated by a channel region of said second conductivity type; a second avalanche injection element having a third active region of said second conductivity type and sharing said second active region with said first avalanche injection element, the second avalanche injection element having a channel region of said first conductivity type; and a common floating gate at least partially overlying said first and second avalanche injection elements. In a further embodiment, the first avalanche element has an N+/P junction, the second avalanche element has a P+/N junction, and the floating gate capacitively coupled to the first and second avalanche elements.

Abstract: A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the avalanche injection element, and to the CMOS inverter. The avalanche injection element is arranged, so as to transfer electrical charge onto the floating-gate electrode. The presence of stored data within the memory cell is indicated by reading a supply voltage V.sub.DD at an output terminal of the inverter. Accordingly, data can be read from the non-volatile memory cell without applying electrical power to the cell.

Abstract: A structure and method for forming an isolation wall in an etched trench are described. The trench walls are covered by a thin silicon oxide layer and the trench conformally filled with an oxy-nitride mixture having a particular range of composition so as to produce a neutral to slight tensile stress in the oxy-nitride relative to silicon. The structure is very simple to fabricate and creates fewer defects in the silicon substrate than prior art techniques. Buried voids in the filled trench are eliminated.

Abstract: A structure and method for forming an isolation wall in an etched trench are described. The trench walls are covered by a thin silicon oxide layer and the trench conformally filled with an oxy-nitride mixture having a particular range of composition so as to produce a neutral to slight tensile stress in the oxy-nitride relative to silicon. The structure is very simple to fabricate and creates fewer defects in the silicon substrate than prior art techniques. Buried voids in the filled trench are eliminated.