Abstract: Quick release couplings for releasably coupling components of a computer to the computer are disclosed. The quick release coupling mechanisms are generally configured to allow tool-less placement of the components relative to the computer. That is, the quick release coupling mechanisms are configured to perform their couplings without using conventional fasteners such as screws, bolts, etc. By eliminating the use of fasteners, the components may be inserted and removed from the computer without using tools (e.g., tool-less). Furthermore, the quick release couplings are easy to maneuver thereby enabling quick and straightforward assembly and disassembly of the components to and from the computer (e.g., quick release). For example, the components may be inserted and removed by a simple pushing or pulling motion, and/or by a simple flick of a latch or handle.

Abstract: Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

Abstract: To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

Abstract: Micro-valves and micro-pumps and methods of fabricating micro-valves and micro-pumps. The micro-valves and micro-pumps include electrically conductive diaphragms fabricated from electrically conductive nano-fibers. Fluid flow through the micro-valves and pumping action of the micro-pumps is accomplished by applying electrostatic forces to the electrically conductive diaphragms.

Abstract: An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.

Abstract: Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.

Abstract: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

Abstract: An apparatus for air-cooling an electronic device is disclosed. A contoured panel channels a flow of air within the housing of an electronic device so as to channel the flow of air more directly over heat producing elements such as the microprocessor and peripheral cards. A sensor can also be employed to determine whether the panel is present and properly placed. If not, measures can be taken to reduce the heat generated by the heat producing elements. For example, a warning can be displayed, or the microprocessor can be instructed to enter sleep mode.

Abstract: The invention provides for a mineral insulating oil having a naphthenic base oil and a paraffinic base oil wherein the naphthenic base oil includes a ratio of total sulfur to basic nitrogen of less than about 80:1. The invention also provides for a mineral insulating oil having a naphthenic base oil, a paraffinic base oil, and an antioxidant agent wherein the naphthenic base oil includes a ratio of total sulfur to basic nitrogen of less than about 80:1. The invention also provides for a process for producing a mineral insulating oil including contacting a naphthenic base oil and a paraffinic base oil wherein the naphthenic base oil includes a ratio of total sulfur to basic nitrogen of less than about 80:1. The invention also provides for a process for producing a mineral insulating oil including contacting a naphthenic base oil, a paraffinic base oil, and an antioxidant agent wherein the naphthenic base oil includes a ratio of total sulfur to basic nitrogen of less than about 80:1.

Abstract: A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial polymer containing silicon that is deposited over a gate conductor layer and covered by a cover layer. The sacrificial polymer layer is patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the polymer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.

Abstract: A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon nanotubes, and then removing the carbon nanotubes to produce the voids. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. Recesses formed in the dielectric for conductors are lined with a non-conformal dielectric film to seal the voids. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

Abstract: An apparatus for air-cooling an electronic device is disclosed. A contoured panel channels a flow of air within the housing of an electronic device so as to channel the flow of air more directly over heat producing elements such as the microprocessor and peripheral cards. A sensor can also be employed to determine whether the panel is present and properly placed. If not, measures can be taken to reduce the heat generated by the heat producing elements. For example, a warning can be displayed, or the microprocessor can be instructed to enter sleep mode.

Abstract: Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the overhang and in the holes until the conformal layer closes off the holes to form a void/seam in each hole. The void/seam in each hole is exposed by etching back a top surface. The void/seam in each hole is extended to the underlying layer.

Abstract: Quick release couplings for releasably coupling components of a computer to the computer are disclosed. The quick release coupling mechanisms are generally configured to allow tool-less placement of the components relative to the computer. That is, the quick release coupling mechanisms are configured to perform their couplings without using conventional fasteners such as screws, bolts, etc. By eliminating the use of fasteners, the components may be inserted and removed from the computer without using tools (e.g., tool-less). Furthermore, the quick release couplings are easy to maneuver thereby enabling quick and straightforward assembly and disassembly of the components to and from the computer (e.g., quick release). For example, the components may be inserted and removed by a simple pushing or pulling motion, and/or by a simple flick of a latch or handle.

Abstract: A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.

Abstract: Structures and methods for operating the same. The structure includes (a) a substrate; (b) a first and second electrode regions on the substrate; and (c) a third electrode region disposed between the first and second electrode regions. In response to a first write voltage potential applied between the first and third electrode regions, the third electrode region changes its own shape, such that in response to a pre-specified read voltage potential subsequently applied between the first and third electrode regions, a sensing current flows between the first and third electrode regions. In addition, in response to a second write voltage potential being applied between the second and third electrode regions, the third electrode region changes its own shape such that in response to the pre-specified read voltage potential applied between the first and third electrode regions, said sensing current does not flow between the first and third electrode regions.

Abstract: A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.

Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Abstract: Methods of forming low-k dielectric layers for use in the manufacture of semiconductor devices and fabricating semiconductor structures using the low-k dielectric material. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.