Abstract: A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface ; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.

Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

Abstract: A method of providing a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, binding a seed layer to the activated sites, and plating the dummy gate on the seed layer. The dummy gate defines a location for the gate conductor. Semiconductor devices having a dummy gate plated thereon to a width of between about 10 to about 70 nanometers are also provided.

Abstract: A method for forming a conductive wire structure for a semiconductor device includes defining a mandrel on a substrate, forming a conductive wire material on the mandrel by atomic layer deposition, and forming a liner material around the conductive wire material by atomic layer deposition.

Abstract: A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites. A metallic conductive material can then be plated on the seed layer to form the gate conductor. Semiconductor devices having a gate conductor plated thereon to a width of between about 1 to about 7 nanometers are also provided.

Abstract: A cubical computer housing assembly comprises first and second ends and four sides, which define an interior compartment for housing the various computer components. The first and second ends are rigidly connected to one another and are slidingly detachable from four sides of the assembly. The interior compartment comprises three parallelepiped portions, one for accommodating a plurality of circuit boards, one for accommodating a heat sink and hard disk drive, and one for accommodating other memory device such as a CD ROM or DVD player. A hard disk drive is slidingly mounted in a frame which is rigidly mounted relative to the first and second ends. A hinged door on which is mounted a printed circuit board can be moved to an open position to provide access to the disk drive for removal and replacement of same.

Abstract: Apparatus for interactively generating a display signal. The apparatus comprises: a receiver (2) for receiving a broadcast signal (15), the broadcast signal comprising a plurality of datastreams each including image data defining a background object (22–270), and control parameters (28–39); a foreground computer generated imagery (CGI) device (3) for generating a foreground computer generated object (CGO); a mixer (4) for combining the foreground CGO with background object image data to generate the display signal; and interaction means (3) for receiving the control parameters from the receiver, monitoring the position of the foreground CGO, and adapting the display signal with reference to the monitored position of the foreground CGO and the received control parameters.

Abstract: A method for implanting gate regions essentially without implanting regions of the semiconductor layer where source/drain regions will be later formed. The method includes the steps of (a) providing (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, (iii) a gate region on the gate dielectric layer, wherein the gate region is electrically insulated from the semiconductor layer by the gate dielectric layer; (b) forming a resist layer on the gate dielectric layer and the gate region; (c) removing a cap portion of the resist layer essentially directly above the gate region essentially without removing the remainder of the resist layer; and (d) implanting the gate region essentially without implanting the semiconductor layer.

Abstract: A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

Abstract: Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.

Abstract: A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed to an oxide deposition bath, thereby causing deposition of oxide on those surfaces. Deposition of oxide on the top surface causes growth of the cap layer in a vertical direction and deposition of oxide on the side surface causes growth of the cap layer in a horizontal direction, thereby forming the beanie structure.

Abstract: A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.

Abstract: A method of exposing images on a wafer having varying topography during lithographic production of microelectronic devices. The method initially includes determining topography of a wafer, dividing the wafer into two or more separate regions based on the wafer topography, and determining desired focus distance for exposing a desired image on each of the separate regions of the wafer. The method then includes exposing a desired image on one of the regions of the wafer at the desired focus distance while blocking remaining regions and exposing a desired image on another of the regions of the wafer at the desired focus distance while blocking remaining regions. The desired focus distance may be different for each of the separate wafer regions.

Abstract: Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.

Abstract: An integrated sweep kit provides for the detection and location of covert electronic eavesdropping devices of both the radiating type (ie. transmitting electromagnetic energy) and the non-radiating type (ie. not transmitting electromagnetic energy). The kit includes at least one non-radiating device sensor for actively transmitting a detection signal, which detection signal is adapted to trigger a response from a normally non-radiating device; and at least one radiating device sensor for passively receiving a signal generated by a radiating device. A synchronization means is used for consecutively activating operation of the non-radiating device sensor and the radiating device sensor during sequential time slots so that the sensors do not interfere with one another.

Abstract: An apparatus for air-cooling an electronic device is disclosed. A contoured panel channels a flow of air within the housing of an electronic device so as to channel the flow of air more directly over heat producing elements such as the microprocessor and peripheral cards. A sensor can also be employed to determine whether the panel is present and properly placed. If not, measures can be taken to reduce the heat generated by the heat producing elements. For example, a warning can be displayed, or the microprocessor can be instructed to enter sleep mode.

Abstract: A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

Abstract: Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

Abstract: A method and apparatus for reduction and prevention of residue formation and removal of residues formed in an immersion lithography tool. The apparatus including incorporation of a cleaning mechanism within the immersion head of an immersion lithographic system or including a cleaning mechanism in a cleaning station of an immersion lithographic system.

Abstract: An apparatus for holding a wafer and a method for immersion lithography. The apparatus, including a wafer chuck having a central circular vacuum platen, an outer region, and a circular groove centered on the vacuum platen, a top surface of the vacuum platen recessed below a top surface of the outer region and a bottom surface of the groove recessed below the top surface of the vacuum platen; one or more suction ports in the bottom surface of the groove; and a hollow toroidal inflatable and deflatable bladder positioned within the groove.