Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.

Abstract: A fabrication method for manufacturing a monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Abstract: A thin film slider with an on-board multi-layer integrated circuit includes a substrate with an air bearing surface and a substantially parallel upper surface spanned by a deposit end. A magnetic head being formed at the deposit end, positioned to magnetically exchange data with a magnetic recording medium that passes beneath the air bearing surface. The upper surface bears an integrated multi-layer accessory circuit, which may be prepared using the CUBE process. Hence, components and vias of the different circuit layers are attached by interconnections that span the edges of the circuit layers. The accessory circuit preferably includes one or more memory devices, such as a cache memory, a DRAM circuit, an EPROM circuit, or another memory circuit appropriate to the application. In embodiments where the magnetic head is a magnetoresistive ("MR") head, the accessory circuit may also include a pre-amplifier and a sensing circuit to support operation of the MR head.

Abstract: A communications system uses a World Wide Web (Web) server to provide multimedia messaging functions over the Internet. Multimedia workstations are interconnected via the public switched telephone network (PSTN). Parties are provided with multimedia mailboxes on message servers that are connected to the PSTN and the Internet. In order to identify the message server on which a called party's mailbox is located, the Web server provides the multimedia number of the called party's message server when a call is made. In addition, the Web server provides the multimedia number of the called party. When a multimedia call is unanswered, the system uses the multimedia number of the message server and the called party multimedia number provided by the Web server to record and store a message for the called party in the called party's mailbox.

Abstract: Compounds with fungicidal properties having formula I ##STR1## wherein W is CH.sub.3 --O--A.dbd.C(-)--CO(V)CH.sub.3 ;A is N or CH;V is O or NH;R.sub.4 and R.sub.5 are independently selected from hydrogen and substituted or unsubstituted alkyl and aryl groups and Q is substituted or unsubstituted aryl groups.

Abstract: A magneto-resistive read head having a "parasitic shield" provides an alternative path for currents associated with sparkovers, thus preventing such currents from damaging the read head. The parasitic shield is provided in close proximity to a conventional magnetic shield. The electrical potential of parasitic shield is held essentially equal to the electrical potential of the sensor element. If charges accumulate on the conventional shield, current will flow to the parasitic shield at a lower potential than would be required for current to flow between the conventional shield and the sensor element. Alternatively, conductive spark gap devices are electrically coupled to sensor element leads and to each magnetic shield. Each spark gap device is brought within very close proximity of the substrate to provide an alternative path for charge that builds up between the sensor element and the substrate to be discharged.

Abstract: Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure.

Abstract: An enhanced electrostatic discharge suppression circuit is disclosed for protecting integrated circuit chips from electrostatic discharges or other potentially damaging voltage transients on an input/output pad. The suppression circuit includes a discharge circuit, electrically coupled to the input/output pad, having a diode comprising a diffusion in a substrate well formed in a substrate. The diffusion is connected to the input/output pad of the integrated circuit. A capacitor is locally provided to couple the substrate well to the substrate. The capacitor is sized to maintain the diode in a forward-bias mode during the electrostatic discharge event, thereby facilitating dissipating of the electrostatic discharge. The capacitor comprises a trench capacitor, which depending upon the configuration, may function as a guard ring for the discharge circuit. Certain beneficial parasitic effects are also discussed in association with integration of a trench capacitor into the suppression circuit.

Abstract: A thin film slider with an on-board multi-layer integrated circuit includes a substrate with an air bearing surface and a substantially parallel upper surface spanned by a deposit end. A magnetic head being formed at the deposit end, positioned to magnetically exchange data with a magnetic recording medium that passes beneath the air bearing surface. The upper surface bears an integrated multi-layer accessory circuit, which may be prepared using the CUBE process. Hence, components and vias of the different circuit layers are attached by interconnections that span the edges of the circuit layers. The accessory circuit preferably includes one or more memory devices, such as a cache memory, a DRAM circuit, an EPROM circuit, or another memory circuit appropriate to the application. In embodiments where the magnetic head is a magnetoresistive ("MR") head, the accessory circuit may also include a pre-amplifier and a sensing circuit to support operation of the MR head.

Abstract: An MR head receives ESD protection from a mechanism that automatically and releasably shorts the MR head whenever a suspension assembly on which the head is mounted is not installed in an HDA. The suspension assembly includes a flexure underlying a load beam, which is connected to an actuator arm. The MR head is mounted to a distal end of the flexure, leads from components of the MR head being brought out in the form of MR wire leads running along the load beam and the support arm to a nearby terminal connecting side tab. The conductors are separated and exposed at a designated point along the flexure to provide a contact region. A shorting bar, which comprises an electrically conductive member attached to the actuator arm, automatically connects the MR wire leads at the contact region when absence of support for the MR head permits the load beam to bend sufficiently toward the shorting bar.

Abstract: Interchip and intrachip electrical discharge suppression connections or networks are disclosed for three-dimensional multichip semiconductor structures. The interchip suppression networks electrically intercouple the power planes of the semiconductor device chips in the structure. This, in combination with conventional intrachip suppression networks present on the external connects or input/output pins of the individual chips in the structure, provides complete power plane-to-power plane, external connect-to-power plane and external connect-to-external connect protection against electrical discharge events, such as an electrostatic discharge occurring during handling and testing of the structure. The interchip electrical discharge suppression networks can be placed on an end layer or end semiconductor chip of the three-dimensional multichip semiconductor structure and connect to individual chips in the structure via an edge surface metallization.

Abstract: A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.

Abstract: A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.

Abstract: An MR head receives ESD protection from a mechanism that automatically and releasably shorts the MR head whenever a suspension assembly on which the head is mounted is not installed in an HDA. The suspension assembly includes a flexure underlying a load beam, which is connected to an actuator arm. The MR head is mounted to a distal end of the flexure, leads from components of the MR head being brought out in the form of MR wire leads running along the load beam and the support arm to a nearby terminal connecting side tab. The conductors are separated and exposed at a designated point along the flexure to provide a contact region. A shorting bar, which comprises an electrically conductive member attached to the actuator arm, automatically connects the MR wire leads at the contact region when absence of support for the MR head permits the load beam to bend sufficiently toward the shorting bar.

Abstract: A laminating adhesive comprising an adhesive composition which comprises(a) An epoxidized block copolymer of the formula(A--B--A.sub.p).sub.n --Y.sub.r --(A.sub.q --B).sub.mwherein Y is a coupling agent or coupling monomers, andwherein A and B are polymer blocks which may be homopolymer blocks of conjugated diolefin monomers, copolymer blocks of conjugated diolefin monomers or copolymer blocks of conjugated diolefin monomers and monoalkenyl aromatic hydrocarbon monomers, andwherein the A blocks have a higher number of aliphatic double bonds between a tertiary carbon atom and either a primary, secondary, or tertiary carbon atom per unit of block mass than do the B blocks, andwherein the A blocks have a molecular weight from about 100 to about 3000 and the B blocks have a molecular weight from about 1000 to about 15,000, andwherein p and q are 0 or 1 and n>0, r is 0 or 1, m.gtoreq.